AMD Adaptive Computing documentation is organized around a set of standard design processes to help you find relevant content for your current development task. All AMD Versal™ adaptive SoC design process Design Hubs and the Design Flow Assistant materials can be found on the Xilinx.com website. This document covers the following design processes:
- System and Solution Planning
Identifying the components, performance, I/O, and
data transfer requirements at a system level.
Includes application mapping for the solution to PS,
PL, and AI Engine. Topics in this document that apply to this design process
- Overview provides an overview of the AI Engine architecture and includes:
- AI Engine Tile Architecture describes the interaction between the memory module and the interconnect and between the AI Engine and the memory module.
- AI Engine Array Interface Architecture is a high-level view of the AI Engine array interface to the PL and NoC.
- AI Engine Architecture describes the processor functional unit and register files.
- AI Engine Configuration and Boot describes configuring the AI Engine array from the processing system during boot and reconfiguration.
- AI Engine Development
- Creating the AI Engine graph and kernels, library use, simulation debugging and profiling, and algorithm development. Also includes the integration of the PL and AI Engine kernels. Topics in this document that apply to this design process include: