Versal Adaptive SoC AI Engine Architecture Manual (AM009)

Document ID
Release Date
1.3 English
The AI Engine array has a single clock domain for all the tiles and array interface blocks. The performance target of the AI Engine array for the –1L speed grade devices is 1 GHz with VCCINT at 0.70V. In addition, the AI Engine array has clocks for interfacing to other blocks. The following table summarizes the various clocks in the AI Engine array and their performance targets.
Table 1. AI Engine Interfacing Clock Domains
Clock Target for -1L Source Relation to AI Engine Clock
AI Engine array clock 1 GHz AI Engine PLL N/A
NoC clock 960 MHz NoC clocking Asynchronous, CDC within NoC
PL clocks 500 MHz PL clocking Asynchronous, CDC within AI Engine array interface
NPI clock 300 MHz NPI clocking Asynchronous