The AI Engine array has performance counters that can be used for profiling. The AI Engine has four performance counters that can be configured to count any of the internal events. It will either count the occurrence of the events or the number of clock cycles between two defined events. The memory module and the PL modules in the PL and NoC array interface tiles each have two performance counters that can be configured to perform similar functions. The following figure shows a high-level logical view of the profiling hardware in the AI Engine tile. The performance control registers and performance counter registers are described in the Versal Adaptive SoC AI Engine Register Reference (AM015).
Figure 1. Logical View of AI Engine Profiling