The AI Engine has several types of
registers. Some of the registers are used in different functional units. This
section describes the various types of registers.
Scalar registers include configuration registers. See the following table for register
Table 1. Scalar Registers
|Number of bits
Table 2. Special Registers
|Number of bits
|Circular buffer start address
|Circular buffer size
|Wide circular buffer size
|Mode control register
|Loop count (PCU)
registers are high-width registers to allow SIMD instructions. The
underlying basic hardware registers are 128-bit wide, prefixed with the letter V.
Two V registers can be grouped to form a 256-bit register prefixed with W. WR, WC,
and WD registers are grouped in pairs to form 512-bit registers (XA, XB, XC, and
XD). XA and XB form the 1024-bit wide YA registers. For all the registers except YD,
the order is LSB from the top of the table to MSB at the bottom of the table. For
YD, the LSBs are from the XD, and the MSBs are from the XB, that
Table 3. Vector Registers
registers are used to store the results of the vector data path. They are 384-bit wide
which can be viewed as 8 vector lanes of 48-bit each. The idea is to have 32-bit
multiplication results and accumulate over those results without bit overflows. The 16
allow up to 216
accumulations. The accumulator registers are prefixed with the letters AM.
Two of them are aliased to form a 768-bit register that is prefixed with BM.
Note: There are two modes of operation. In the first mode, the multiplication
results are post-added into 8 accumulators using 16 post additions before the
accumulation. In the second mode, the multiplication results are post-added into 16
accumulators using 8 post additions before the accumulation.
Table 4. Accumulator Registers