The following table shows the revision history for this document.
Section | Revision Summary |
---|---|
8/18/2023 Version 1.3 | |
Performance | Changed the NoC clock in the Table 1 from 800 MHz to 960 MHz based on the -1L speed grade in the Network on Chip Switching Characteristics table in the Versal AI Core Series Data Sheet: DC and AC Switching Characteristics (DS957). |
Memory Mapped AXI4 Interconnect | Updated Figure 1. |
AI Engine Tile Program Memory | Updated the discussion on how to handle the arbitration logic. |
AI Engine Interfaces | Updated data memory in Figure 1. |
AI Engine Events | Added ECC Scrubbing Event discussion. |
AI Engine Array Interface | Changed NoC interface in the Table 2 from 800 MHz to 960 MHz based on the -1L speed grade in the Network on Chip Switching Characteristics table in the Versal AI Core Series Data Sheet: DC and AC Switching Characteristics (DS957). |
AI Engine to Programmable Logic Interface | Added boundary logic discussion and reference information. |
Arithmetic Logic Unit, Scalar Functions, and Data Type Conversions | Updated fixed point value range. |
AI Engine Array Configuration | Added the awl1545173526811.html#awl1545173526811__title-config-time section. |
10/21/2021 Version 1.2 | |
AI Engine Tile Architecture | Updated definitions in Figure 1 and Figure 2. |
AXI4-Stream Interconnect | Added port handler and packet-switched streams information and a packet header diagram. |
AI Engine Array Interface | Added information on PL-AI Engine array interface bit width. |
Functional Overview | Described how cfloat is not directly supported
by the AI Engine vector processor. |
Arithmetic Logic Unit, Scalar Functions, and Data Type Conversions | Updated scalar floating-point support. |
Fixed-Point Vector Unit | Added information on vector comparison implementation in a fixed-point vector. |
Floating-Point Vector Unit | Added information on how and where comparison is implemented in floating-point vectors and information on floating-point exceptions. |
4/22/2021 Version 1.1 | |
General | Added links to Versal Adaptive SoC AI Engine Register Reference (AM015) |
Memory Error Handling | Clarified how the performance counter during memory-mapped AXI4 access works. |
Arithmetic Logic Unit, Scalar Functions, and Data Type Conversions | Added implementation notes on managing the Float2fix conversion for overflow exceptions. |
7/16/2020 Version 1.0 | |
Initial release. | N/A |