Attributes

TRUE: Cascades the input and output delay of a NIBBLESLICE, which doubles the available delay from 512 taps/625 ps to 1024 taps/1250 ps. Cascading is only possible for the receiver and renders the TX datapath of that NIBBLESLICE inoperable outside of its output delay used for the cascading. When changing the delay, it is recommended to store half of the desired delay value in the input delay and half in the output delay.

FALSE: No cascade, only the input delay is used for the receiver.

Used with the RX_GATING attribute and the PHY_RDEN port to gate the capture clock entering on NIBBLESLICE[0] or from inter-byte or inter-nibble clocking.

The capture clock must be continuous (not a strobe) to set CONTINUOUS_DQS = TRUE. Because the capture clock is continuous and because there is no timing requirement between PHY_RDEN and the capture clock, the gate enable and disable is not cycle accurate to the capture clock (RX_GATING = ENABLE, CONTINUOUS_DQS = TRUE in this case). In contrast, when RX_GATING = ENABLE and CONTINUOUS_DQS = FALSE, gate enable and disable can be trained to be deterministic.

Setting CONTINUOUS_DQS = TRUE requires that two capture clock cycles be received prior to receiving data to prevent data loss.

See the PHY_RDEN description in Ports and refer to Bidirectional Datapath for more information.

TRUE: In addition to the normal quarter delays applied to the strobe, a coarse delay is applied. Set CRSE_DLY_EN to TRUE if RX_CLK_PHASE_P/N = SHIFT_90, the interface receives edge-aligned clock and data, and the interface is below 1 GHz. Using coarse delays requires that SELF_CALIBRATE = ENABLE and that both RX_CLK_PHASE_P and RX_CLK_PHASE_N be set to the same value as one another (both SHIFT_90 or both SHIFT_0).

FALSE: A coarse delay will not be applied.

The CRSE delay can only be used with a low frequency (200 MHz – 1 GHz) PLL_CLK, edge-aligned source-synchronous receiver interface to center the strobe to data.

• If CASCADE_x = TRUE, the maximum value of DELAY_VALUE_x extends from 625 ps to 1250 ps.
• For NIBBLESLICEs with TX_OUTPUT_PHASE_90_x = TRUE, the DELAY_VALUE_x must be set to 0.
• For NIBBLESLICEs in a nibble with RX_CLK_PHASE_<P|N> = SHIFT_90, at least one of the nibbleslices within the nibble must have DELAY_VALUE_x = 0.
• A non-zero delay requires SELF_CALIBRATE = ENABLE.

For interfaces with PLL_CLK below 500 MHz, DELAY_VALUE is not supported. Consequently, delays will need to be updated using the CNTVALUEIN, CE, INC, and LD ports. See Controlling Delays for more information.

TRUE: Disables VTC on input delays.

FALSE: Enables VTC on input delays. Following the steps outlined in Controlling Built-in Self-Calibration is still required for VTC to operate.

TRUE: Disables VTC on output delays.

FALSE: Enables VTC on output delays. Following the steps outlined in Controlling Built-in Self-Calibration is still required for VTC to operate.

TRUE: Disables VTC on QTR delays.

FALSE: Enables VTC on QTR delays. Following the steps outlined in Controlling Built-in Self-Calibration is still required for VTC to operate.

LOCAL: Set to LOCAL if the strobe is sourced from the connecting IOB, if its source and destination nibble are the same (the latter would require TXRX_LOOPBACK_x = TRUE for NIBBLESLICE[x]), or if SERIAL_MODE = TRUE.

EXTERN: Set to EXTERN if the strobe enters through inter-byte clocking.

DQS_SRC can be set to either value for nibbles receiving a strobe through inter-nibble clocking.

ENABLE: Enables inter-byte clocking to a numerically lower nibble.

DISABLE: Disables inter-byte clocking to a numerically lower nibble.

ENABLE: Enables inter-byte clocking to a numerically higher nibble

DISABLE: Disables inter-byte clocking to a numerically higher nibble

TRUE: Enables sourcing the n-side of the strobe from inter-nibble clocking.

FALSE: Disables sourcing the n-side of the strobe from inter-nibble clocking.

TRUE: Enables sourcing the p-side of the strobe from inter-nibble clocking.

FALSE: Disables sourcing the p-side of the strobe from inter-nibble clocking.

ASYNC: Set to ASYNC if the read and write clocks of the FIFO in NIBBLESLICE[x] are the same frequency but phase independent.

SYNC: Set to SYNC if the read and write clocks of the FIFO in NIBBLESLICE[x] are the same clock. SYNC requires a continuous receive data clock.

BYPASS: Set to BYPASS for the FIFO in NIBBLESLICE[x] to forward the data to the fabric (it is not stored in the FIFO like in the ASYNC and SYNC settings). A zero cycle path is possible here. . BYPASS requires a continuous receive data clock.

TRUE: Inverts the incoming strobe from the IOB to NIBBLESLICE[0], which also affects all nibbles that the clock is routed to as a result of inter-nibble/byte clocking. INV_RXCLK only affects the n-clk.

FALSE: Strobe is not inverted. This is the only supported INV_RXCLK value when DQS_SRC = EXTERN

SHIFT_0: Set to SHIFT_0 to not apply a phase shift to the n-clk.

SHIFT_90: Set to SHIFT_90 to apply a positive 90° phase shift (relative to the data) to the n-clk. This phase shift is not retained for inter-nibble clocking. Setting RX_CLK_PHASE_N = SHIFT_90 requires that SELF_CALIBRATE = ENABLE. DELAY_VALUE_x of all NIBBLESLICEs must be set to 0 in nibbles where RX_CLK_PHASE_N = SHIFT_90.

SHIFT_0: Set to SHIFT_0 to not apply a phase shift to the p-clk.

SHIFT_90: Set to SHIFT_90 to apply a positive 90° phase shift (relative to the data) to the p-clk. This phase shift is not retained for inter-nibble clocking. Setting RX_CLK_PHASE_P = SHIFT_90 requires that SELF_CALIBRATE = ENABLE. DELAY_VALUE_x of all NIBBLESLICEs must be set to 0 in nibbles where RX_CLK_PHASE_P = SHIFT_90.

ENABLE: Enables BISC (proper assertion of EN_VTC, RX_EN_VTC, and TX_EN_VTC is still required)

DISABLE: Disables BISC.

TRUE: Set to TRUE for interfaces where data is received without an accompanying source synchronous clock (strobe). In this case, the capture clock is generated internally from the PLL_CLK input.

FALSE: Set to FALSE for source-synchronous interfaces.

T: Set to T if using the T input (combinatorial path from the PL) as the tristate control signal for NIBBLESLICE[x]. If TX_DATA_WIDTH = 2, only T (not PHY_WREN) can be used as the tristate control signal.

PHY_WREN: Set to PHY_WREN if using the PHY_WREN input as the tristate control signal for NIBBLESLICE[x]. The serialized and inverted PHY_WREN is synchronized with the TX data. Each bit of PHY_WREN controls the tristate for two bits of data.

T and PHY_WREN can both be applied to the same NIBBLESLICE, and the NIBBLESLICE selects which one to use based on its TBYTE_CTL_x setting.

TRUE: Set to TRUE to loop back the TX output to RX input of the same NIBBLESLICE[x]. The TX output will still reach the IOB. A buffer (IBUF, OBUF, IOBUF, or a variant of one of the three) must be used for loopback to work. Connect the net from XPHY.O0[x] to the input of an OBUF, IOBUF, or variant of one of the two. Alternatively, connect the output net from an IBUF, IOBUF, or a variant of one of the two to XPHY.DATAIN[x]. Regardless of which net is used, only use one buffer (IBUF, OBUF, or variant) in this path.

FALSE: Set to FALSE for no loopback and for all unused nibbleslices.

TXRX_LOOPBACK_# is not supported when SERIAL_MODE = TRUE. See Controlling TX to RX Loopback for more information.

If TX_DATA_WIDTH = 2, any IOBs connected to the nibble cannot use PRE_EMPHASIS.

DISABLE:The TX datapath of NIBBLESLICE[0], NIBBLESLICE[2], NIBBLESLICE[3], NIBBLESLICE[4], and NIBBLESLICE[5] are not gated. NIBBLESLICE[1] cannot be gated through this attribute, regardless of its setting.

ENABLE: Use PHY_WREN to gate the TX datapath of NIBBLESLICE[0], NIBBLESLICE[2], NIBBLESLICE[3], NIBBLESLICE[4], and NIBBLESLICE[5]. NIBBLESLICE[1] cannot be gated.

1'b0: Sets the TX IOB value associated with NIBBLESLICE[x] during configuration and reset (in this case, TX_RST[x] = 1 or RST = 1) to 1'b0.

1'b1: Sets the TX IOB value associated with NIBBLESLICE[x] during configuration and reset (in this case, TX_RST[x] = 1 or RST = 1) to 1'b1.

1'b0: Sets the tristate control signal during configuration and reset (in this case, TX_RST[x] = 1 or RST = 1) to 1'b0.

1'b1: Sets the tristate control signal during configuration and reset (in this case, TX_RST[x] = 1 or RST = 1) to 1'b1.

TRUE: Applies a positive 90° phase shift to the TX output of NIBBLESLICE[x]. DELAY_VALUE_x should be set to 0 when TX_OUTPUT_PHASE_90_x = TRUE.

FALSE: Set to FALSE to not apply the 90° shift.

Used for center-aligned DDR TX signals where tristate control is required. Only applicable when TBYTE_CTL_x = PHY_WREN. Each NIBBLESLICE being tristated must have its associated DELAY_VALUE_x set to 0.

TRUE: Applies a positive 90° phase shift to T_OUT[x].

FALSE: Does not apply the 90° phase shift.