Each XPIO bank has two XPLLs. Each XPLL has four user-controlled clock outputs (XPLL.CLKOUT<0-3>) to the programmable logic (PL) and a dedicated, high-speed clock connection (XPLL.CLKOUTPHY) to all XPHY nibbles in an XPIO bank. For more information on XPLLs, see the Versal ACAP Clocking Resources Architecture Manual (AM003). The following tables summarize XPHY clocking ports and attributes. For more complete descriptions, see Ports and Attributes.
|PLL_CLK||Input||Clocks the XPHY interface|
|CTRL_CLK||Input||RIU/delay line/BISC clock|
|FIFO_RD_CLK||Input||The FIFO read clock|
|CLK_FROM_OTHER_XPHY||Input||Inter-byte clock input|
|NCLK_NIBBLE_IN||Input||N-clk input for inter-nibble clocking|
|PCLK_NIBBLE_IN||Input||P-clk input for inter-nibble clocking|
|FIFO_WR_CLK||Output||The FIFO write clock. Generated internally.|
|CLK_TO_LOWER||Output||Inter-byte clock output to certain numerically lower nibbles (with one exception to a numerically higher nibble).|
|CLK_TO_UPPER||Output||Inter-byte clock output to certain numerically higher nibbles.|
|NCLK_NIBBLE_OUT||Output||N-clk output for inter-nibble clocking|
|PCLK_NIBBLE_OUT||Output||P-clk output for inter-nibble clocking|
|Strobe/Capture clock||Input (RX)
|Strobes/capture clocks can be received through
the IOB to NIBBLESLICE or through inter-nibble/inter-byte
clocking. Within the XPHY the strobe is separated into a p-clk and
n-clk, which then can be used for inter-nibble clocking and data
For source-synchronous receive interfaces (implying SERIAL_MODE = FALSE), the strobe/capture clock is received with the data with a known phase relationship. For other receive interfaces (implying SERIAL_MODE = TRUE), the capture clock is generated within the XPHY from PLL_CLK. Inter-nibble and inter-byte clocking aren't supported when SERIAL_MODE = TRUE
|Clock||I/O||Connection (TX)||Connection (RX)|
|CTRL_CLK||Input||Does not need to come from a specific clock source||Does not need to come from a specific clock source.|
|FIFO_RD_CLK||Input||–||Depends on FIFO_MODE_x. Refer to Controlling FIFO Modes.|
|CLK_FROM_OTHER_XPHY||Input||–||If receiving an inter-byte clock, connect to the applicable CLK_TO_LOWER or CLK_TO_UPPER of the source nibble sending the inter-byte clock.|
|PCLK_NIBBLE_IN, NCLK_NIBBLE_IN||Input||–||If receiving inter-nibble clocks, connect PCLK_NIBBLE_OUT of the source nibble to PCLK_NIBBLE_IN of the destination nibble. Do the same for NCLK_NIBBLE_OUT and NCLK_NIBBLE_IN.|
|FIFO_WR_CLK||Output||–||Generated internally from the strobe or in the case of SERIAL_MODE = TRUE, from PLL_CLK.|
|CLK_TO_LOWER, CLK_TO_UPPER||Output||–||If sending an inter-byte clock, connect the applicable CLK_TO_LOWER or CLK_TO_UPPER of the source nibble to CLK_FROM_OTHER_XPHY of the destination nibble receiving the inter-byte clock.|
|PCLK_NIBBLE_OUT, NCLK_NIBBLE_OUT||Output||–||If sending inter-nibble clocks, connect PCLK_NIBBLE_OUT of the source nibble to PCLK_NIBBLE_IN of the destination nibble. Do the same for NCLK_NIBBLE_OUT and NCLK_NIBBLE_IN.|
|Strobe/Capture clock||Output or input, depending on which perspective: RX (input) or TX (output).||Send through one of the D<0-5> inputs, after which it will be output to the IOB by the corresponding O0[x] bit.||For source-synchronous interfaces, a
strobe/capture clock must be received by NIBBLESLICE (DATAIN),
inter-nibble clocking (see Table 1 for the ports), or inter-byte clocking
(see Table 1 for the ports). If a
strobe/capture clock is received on NIBBLESLICE, regardless of
whether it is single-ended or differential, DELAY_VALUE_0 (and only
DELAY_VALUE_0) must be set to
If SERIAL_MODE = TRUE, the capture clock is generated from the PLL_CLK input for each nibble in the interface. Inter-nibble and inter-byte clocking are not supported when SERIAL_MODE = TRUE.
|CONTINUOUS_DQS||Along with RX_GATING, determines if and how the strobe is gated.|
|DQS_SRC||Determines where the strobe is being received from (NIBBLESLICE, inter-nibble clocking, inter-byte clocking, or PLL_CLK for serial mode).|
|EN_CLK_TO_LOWER||Enables outputting the strobe to certain numerically lower nibbles (inter-byte clocking).|
|EN_CLK_TO_UPPER||Enables outputting the strobe to certain numerically higher nibbles (inter-byte clocking).|
|EN_OTHER_NCLK||Enables sourcing the n-side of the strobe from inter-nibble clocking.|
|EN_OTHER_PCLK||Enables sourcing the p-side of the strobe from inter-nibble clocking.|
|INV_RXCLK||Inverts the incoming strobe to NIBBLESLICE.|
|REFCLK_FREQUENCY||Set to the frequency of PLL_CLK.|
|RX_CLK_PHASE_P, RX_CLK_PHASE_N||Controls strobe (p-clk and n-clk in this case) centering for source-synchronous interfaces.|
|RX_GATING||Along with CONTINUOUS_DQS, determines if and how the strobe is gated.|
|TX_GATING||Uses PHY_WREN to gate the transmit data and/or outgoing strobe/capture clock. NIBBLESLICE cannot be affected by TX_GATING.|
|TX_OUTPUT_PHASE_90_<0-5>||Used to center the strobe/capture clock to data on the transmitter side. Applied to the NIBBLESLICE(s) sending the strobe/capture clock, causing it to be center-aligned to the data.|
When transmit interfaces are placed within a triplet a dedicated cascade path exists from the CLKOUT0 clock output to XPLLs located within adjacent XPIO banks without the need for any clock buffers. In the Advanced IO Wizard, XPLL's can use the dedicated cascades when placed in up to 3 adjacent banks by selecting "Multi Banks are part of a Triplet". The cascaded CLKOUT0 routing delays will have a fixed delay based on the speed grade selected. To roughtly compensate for the dedicated routing delays the Advanced IO Wizard will use a negative phase shift for CLKOUT0_PHASE. Timing analysis of the cascaded delays will be needed to determine the exact delay and therefore the optimal phase shift settings for CLKOUT0_PHASE.
While transmit interface clocking is sourced from XPLLs, receiver clocking for source-synchronous interfaces can take advantage of inter-nibble and inter-byte clocking for forwarding the strobe. If an interface spans more than one nibble, then inter-nibble and/or inter-byte clocking can be used to route the strobe to other nibbles:
- Inter-nibble clocking is supported within nibble-pairs, as shown in the following figure. Nibble-pairs are XPHY nibbles (0,1), (2,3), (4,5), and (6,7)
- Inter-byte clocking is supported between specific XPHY nibbles
within an XPIO bank, as shown in the table below. While inter-nibble clocking
can only occur between two nibbles, inter-byte clocking can forward a strobe
further by using each nibble receiving the inter-byte clock to also forward it.
Nibbles receiving a clock through inter-byte clocking can generate an
inter-nibble clock, though nibbles receiving an inter-nibble clock cannot use it
to generate an inter-byte clock. CLK_FROM_OTHER_XPHY of the source nibble
starting the inter-byte clocking should be set to
- XPHY nibble 8 is not part of a nibble-pair and thus is not capable of inter-nibble clocking, but can receive an inter-byte clock from XPHY nibble 6. Use CLK_TO_LOWER when performing inter-byte clocking from XPHY nibble 6 to XPHY nibble 8. This is the exception to the CLK_TO_LOWER/CLK_TO_UPPER naming scheme.
- When SERIAL_MODE = TRUE, inter-nibble/byte clocking is not supported. Instead, each nibble generates its own capture clock from the PLL_CLK input.
- Inter-nibble and inter-byte clocking can only occur between nibbles in the same bank and cannot be connected to the programmable logic (PL).
- Inter-byte clocking is received/sent before the coarse and quarter delays. Thus, an inter-byte clock passes through both delay blocks in the destination nibble, and neither of them in the source nibble.
- Inter-nibble clocking is received/sent after the coarse delay, but before the quarter delay. Thus, an inter-nibble clock passes through the coarse delay in the source nibble, and the quarter delay in the destination nibble.
- NIBBLESLICEs are aligned to each other (assuming BISC is being used), but word alignment is not guaranteed. Using inter-nibble and/or inter-byte clocking can further negatively affect word alignment.
XPLL placement in the following figure is representative, the XPLL locations varies (with respect to nibbles).
Figure 1 has been translated into a table, as follows.
|XPHY Nibble||Can Route To (Through Inter-nibble Clocking)||Can Route To (Through Inter-byte Clocking)||Can Route To (Through Inter-byte, Inter-nibble, or a Combination of the Two)|
|2||3||0, 4||0, 1, 3, 4, 5, 6, 7, 8|
|3||2||1, 5||0, 1, 2, 4, 5, 6, 7|
|4||5||2, 6||0, 1, 2, 3, 5, 6, 7, 8|
|5||4||3, 7||0, 1, 2, 3, 4, 6, 7|
As shown in the clocking figures, within a bank there are two types of clock inputs that serve two different purposes:
- Global Clock (GC): Clock input with dedicated clock routing designed to have low skew, low duty cycle distortion, and improved jitter resistance. As such, it is recommended for external clocks to enter through GC pins. For interfaces that use XPHY, the GC pins are typically used as the clock source for the XPLLs, which in turn clock the XPHY. GCs can reach all XPLLs in an XPIO bank as well as XPLLs in the adjacent banks.
- XCC: Strobe input for XPHY receive interfaces
- Both GC and XCC: These pins can act as GCs and/or XCCs
Refer to Versal ACAP Clocking Resources Architecture Manual (AM003) for a more detailed explanation of GC and XCC pins.
The following figure shows the XCC and GC pins that can accept a clock and the NIBBLESLICEs with which they are associated. Clocks entering on GC or XCC inputs (as opposed to data entering on those pins), regardless of whether single-ended or differential, must enter the I/O pin associated with NIBBLESLICE. If the clock is differential, the complementary side of the clock (incoming on the I/O pin associated with NIBBLESLICE) should be connected to the same differential buffer as the signal incoming to the I/O pin of NIBBLESLICE. Because NIBBLESLICE is the only NIBBLESLICE that is capable of connecting to the strobe circuitry, NIBBLESLICE's involvement in strobe routing ends with the buffer. Recall that because each NIBBLESLICE routes to a specific pin, receiving a differential signal (regardless of whether clock or data) consumes the pins and RX datapaths of both NIBBLESLICEs. When NIBBLESLICE receives a clock, it is routed through the GC and/or XCC circuitry (depending on its usage and the capabilities of the pin) and the normal RX datapath.
Because there are two XPLLs per bank, one bank can support two data rates. Source-synchronous (implying SERIAL_MODE = FALSE) and SERIAL_MODE = TRUE interfaces can exist in the same bank, but each nibble in its respective interface must be configured as only source-synchronous or only SERIAL_MODE = TRUE.