Controlling Built-in Self-Calibration

The only attribute required to run BISC is SELF_CALIBRATE = ENABLE. The following table shows BISC-related attributes and how they are overridden if BISC is not used (SELF_CALIBRATE = DISABLE). For more complete attribute descriptions, see Attributes.

Table 1. BISC-Related Attributes
Attribute	Description	Effect From SELF_CALIBRATE = DISABLE
CRSE_DLY_EN	Enables CRSE delays	Coarse delays are not used.
DELAY_VALUE_<0-5>	Sets the initial input and output delay line value in each NIBBLESLICE.	DELAY_VALUE_<0-5> loads a zero delay to input and output delays. However, delays can still be loaded from the PL.
DIS_IDLY_VT_TRACK	Disables VTC on input delays	Disables VTC on input delays
DIS_ODLY_VT_TRACK	Disables VTC on output delays	Disables VTC on output delays
DIS_QDLY_VT_TRACK	Disables VTC on QTR delays	Disables VTC on QTR delays
RX_CLK_PHASE_N, RX_CLK_PHASE_P	Controls strobe (p-clk and n-clk in this case) centering for source-synchronous interfaces	RX_CLK_PHASE_N and RX_CLK_PHASE_P cannot be set to SHIFT_90

The following table shows how to control BISC.

Table 2. Controlling BISC Steps Summary
BISC Step	Controlled by	Other Considerations	Common to All
Alignment	Assert RX_EN_VTC and TX_EN_VTC during the reset sequence to perform alignment. Refer to Reset Sequence.	Alignment is only performed once upon completion of the reset sequence. To re-perform alignment, reset the XPHY.	SELF_CALIBRATE must be set to TRUE for any BISC steps to occur BISC is considered completed when: If the interface is using all steps of BISC, when PHY_RDY asserts If the interface is using BISC without VTC, when DLY_RDY asserts If the interface is not using BISC, then DLY_RDY asserting indicates that delays can be changed, but not that alignment and delay calibration are complete. Because BISC is not used in this scenario, it never starts or completes. When simulating, some of the BISC control ports (BISC_START_IN, BISC_STOP_IN, BISC_START_OUT, and BISC_STOP_OUT) must be daisy chained with other nibbles for BISC to be supported. The daisy chain is agnostic to the order in which nibbles are connected, and unused nibbles do not need to be part of the daisy chain. For more information, see Ports.
Delay Calibration	Assert RX_EN_VTC and TX_EN_VTC during the reset sequence to perform delay calibration. Refer to Reset Sequence. When DLY_RDY asserts, both BISC alignment and delay calibration are complete. From this point forward delays can be changed. If multiple nibbles comprise an interface, the assertion time for DLY_RDY can vary for each nibble. Within simulation, the assertion time of DLY_RDY does not vary for each nibble in an interface, but varies as the XPHY configuration and connections change. DLY_RDY can take up to 1.3 ms to assert
VTC	After PHY_RDY asserts, the interface is ready to undergo VTC When EN_VTC = 1, QTR delays and the delay within the tristate NIBBLESLICE undergo VTC. This is not dependent upon RX/TX_EN_VTC. VTC on the tristate signal is not supported on NIBBLESLICEs affected by TBYTE_CTRL_# = T, only for TBYTE_CTRL_# = PHY_WREN. When EN_VTC = 1 and the relevant RX/TX_EN_VTC = 1, input and output delays also undergo VTC For output delays, VTC compensates for the value set in DELAY_VALUE_#. For input delays, the taps that VTC operates on is not as straightforward due to align_delay. See Controlling Delays for more information on how align_delay and DELAY_VALUE_# interact with VTC for input delays. If external calibration is not required and VTC is being used, tie off EN_VTC = 1	Applied to input, output, and quarter delays Can be disabled through the DIS_IDLY_VT_TRACK (input delays), DIS_ODLY_VT_TRACK (output delays), and DIS_QDLY_VT_TRACK (QTR delays) attributes Coarse delays cannot undergo VTC

Important: The DELAY_VALUE_x attribute and VTC are not supported if REFCLK_FREQUENCY is less than 500 MHz. In this scenario, EN_VTC should be tied to 0.

The steps before/after changing delays differ if PHY_RDY was asserted for the first time, as described in the following sequences. If not using VTC, refer to the Controlling Delays section for how to change delay values.

The following sequence and figure show the before/after steps of changing delay values on NIBBLESLICE[x] after PHY_RDY is asserted for the first time:

Start with EN_VTC, RX_EN_VTC, and TX_EN_VTC asserted.
Deassert RX_EN_VTC and TX_EN_VTC.
After RX_EN_VTC and TX_EN_VTC have been deasserted, wait ten CTRL_CLK cycles.
Modify delay values (see Controlling Delays).
Wait another ten CTRL_CLK cycles, then reassert RX_EN_VTC and TX_EN_VTC.
The XPHY is ready to undergo VTC and can be operated normally.

Figure 1. Changing Delay Values After PHY_RDY is Asserted for the First Time

The following sequence and figure show the before/after steps of changing delay values on NIBBLESLICE[x] before PHY_RDY is asserted for the first time:

Start with EN_VTC deasserted, and RX_EN_VTC and TX_EN_VTC asserted.
After DLY_RDY asserts, deassert RX_EN_VTC and TX_EN_VTC.
After the relevant RX_EN_VTC and TX_EN_VTC is deasserted, wait ten CTRL_CLK cycles.
Modify delay values (see Controlling Delays).
Wait another ten CTRL_CLK cycles, then assert EN_VTC, RX_EN_VTC, and TX_EN_VTC.
After PHY_RDY asserts, the XPHY is ready to undergo VTC and can be operated normally.

Figure 2. Changing Delay Values Before PHY_RDY is Asserted for the First Time