Controlling IBUF_DISABLE and DYN_DCI

Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)

Document ID
AM010
Release Date
2024-03-18
Revision
1.5 English

IBUF_DISABLE and DYN_DCI are signals used for power saving. By connecting these signals to an applicable buffer, the buffer and/or its DCI can be turned off, resulting in power savings. The behavior of IBUF_DISABLE and DYN_DCI is dependent upon three factors:

  1. The ODT_SRC_# attribute.
  2. The IBUF_DIS_SRC_# attribute.
  3. The odt_# bus of the NIBBLE_CTRL2 register. (Denoted by NIBBLE_CTRL2.odt_# below. See Register Interface Unit for more information on the NIBBLE_CTRL2 register.)

The following table shows the behavior of IBUF_DISABLE and DYN_DCI with respect to the three factors above. Note that DYN_DCI is expected to be connected to DCITERMDISABLE of the buffer (so DYN_DCI being 1 turns off ODT), and IBUF_DISABLE is expected to be connected to IBUFDISABLE of the buffer (so IBUF_DISABLE being 1 turns off the receiver). When Controlled from the PL is listed, this just means the PL signal should be connected to the applicable buffer input, instead of the XPHY signal being connected to the buffer. When PHY SM is listed, this refers to a state machine (SM) within the XPHY that controls DYN_DCI and IBUF_DISABLE. The state machine operates as follows:

  1. Transitions from 1 to 0 after two cycles (with frequency equal to PLL_CLK/RX_DATA_WIDTH) after PHY_RDEN is asserted.
  2. Stays 0 for a programmable number of cycles after PHY_RDEN is deasserted (determined by the RD_IDLE_COUNT register and the clock being the same as the aforementioned clock).
  3. After the wait, transitions from 0 to 1.
Table 1. IBUF_DISABLE and DYN_DCI Control
ODT_SRC_# IBUF_DIS_SRC_# NIBBLE_CTRL2.odt_# DYN_DCI IBUF_DISABLE
X X X 1 1 1 1
INTERNAL INTERNAL 0 PHY SM controlled 2 PHY SM controlled 2
INTERNAL 3 INTERNAL 1 0 0
INTERNAL EXTERNAL 0 PHY SM controlled 2 Controlled from the PL
INTERNAL EXTERNAL 1 0 Controlled from the PL
EXTERNAL 4 INTERNAL 0 Controlled from the PL PHY SM controlled 2
EXTERNAL INTERNAL 1 Controlled from the PL 0
EXTERNAL EXTERNAL X Controlled from the PL Controlled from the PL
  1. This row represents the power-on state (the receiver is off and ODT is not active).
  2. PHY state machine (SM): transitions 1 → 0 two cycles after (with frequency equal to PLL_CLK/RX_DATA_WIDTH) PHY_RDEN is asserted, then stays 0 for a programmable number of cycles after PHY_RDEN is deasserted (determined by the RD_IDLE_COUNT register and the clock being the same as the aforementioned clock). After the wait, it goes to 1.
  3. For applications where no PL power exists, this configuration should be used.
  4. For applications using the PL, use this configuration to save receiver power while the bus is idle.

If ODT_SRC_#, IBUF_DIS_SRC_#, and NIBBLE_CTRL2.odt# are set such that "Controlled from the PL" is listed above, the respective IBUF_DISABLE/DYN_DCI is controlled by PHY_RDEN. This is done by ORing all bits of PHY_RDEN together, after which the result (a 1 or 0) is broadcast to all bits of the applicable IBUF_DISABLE and/or DYN_DCI.