Four types of delays exist within an XPHY. However, only input and output
delays can be changed through the programmable logic (PL), using CE, INC, LD,
CNTVALUEIN, and RXTX_SEL to do so.
Note: A tap is the smallest amount of delay that a delay
line can produce. For information on tap specifications, see
Versal
AI Core Series Data Sheet: DC and AC Switching
Characteristics (DS957).
- Input delays
- Input delays can delay incoming serialized data up to 512 taps (0–511 taps), with a minimum of 625 ps of available delay. Input delays can be increased to 1024 taps (0–1023 taps) for a minimum of 1250 ps of available delay by cascading the output delay of an XPHY NIBBLESLICE to the end of its input delay. For more information on cascading, see the CASCADE_<0–5> attribute.
- Output delays
- Output delays can delay outgoing serialized data up to 512 taps (0–511 taps), with a minimum of 625 ps of available delay.
- Coarse (CRSE) delay
- The CRSE delay is only used in low frequency (200 MHz -
1 GHz PLL_CLK), source-synchronous receive interfaces and only applied
to the strobe. It cannot be controlled through the PL.
- Intended for edge-aligned source-synchronous interfaces
- Enabled through CRSE_DLY_EN
- Requires SELF_CALIBRATE = ENABLE
- Quarter (QTR) delays
- QTR delays are applied to the p-clk and n-clk. This is
in contrast to CRSE delays, which are applied to the strobe. Cannot be
controlled through the PL. For more information on the p-clk and n-clk,
see Clocking.
- Requires SELF_CALIBRATE = ENABLE