Versal devices have
dedicated registers in the XIOL to implement input DDR registers. This feature is used
by instantiating the IDDRE1 primitive. The IDDRE1 primitive supports the following modes
of operation:
- OPPOSITE_EDGE
- Traditional input DDR solution. Data is presented to Q1 on the rising edge and Q2 on the falling edge.
- SAME_EDGE
- Data is presented to the device logic on the same clock edge.
- SAME_EDGE_PIPELINED
- Data is presented to the device logic on the same clock edge. Removes the separated effect but incurs clock latency.
Figure 1. IDDRE1 Primitive
| Attribute | Values | Description |
|---|---|---|
| DDR_CLK_EDGE | OPPOSITE_EDGE, SAME_EDGE, SAME_EDGE_PIPELINED | Sets the IDDRE1 mode of operation with respect to the clock edge |
| Port | I/O | Description |
|---|---|---|
| Q1, Q2 | Output | IDDRE1 register outputs |
| C | Input | Clock input pin |
| CB | Input | Inverted clock input pin when IS_C_INVERTED = 0 and IS_CB_INVERTED = 0 |
| D | Input | Register input from IOB |
| R | Input | Asynchronous High reset |