This section refers to the FIFO in the RX datapath. The RX datapath FIFO can operate in three modes:
- FIFO_MODE_x = SYNC
- Both read and write sides of the FIFO in NIBBLESLICE[x] share the same clock.
- FIFO_MODE_x = ASYNC
- The read and write clocks of the FIFO in NIBBLESLICE[x] share the same frequency, but can be phase independent.
- FIFO_MODE_x = BYPASS
- Forwards the data and FIFO write clock in NIBBLESLICE[x] to the programmable logic.
The following figure is representative of the FIFO operation for SYNC and ASYNC.
Figure 1. FIFO in RX Datapath (SYNC, ASYNC)
For BYPASS, as shown in the following figure, FIFO_EMPTY is always High and FIFO_RD_CLK is not used. For timing purposes the FIFO_RD_CLK must be left unconnected or connected to a static value to avoid the invalid timing of FIFO_RD_CLK which can alter a design's performance. In BYPASS mode, the internally generated FIFO_WR_CLK is timed when clock constraints are applied to the DQS/Strobe pin by the Advanced I/O Wizard.
Figure 2. FIFO in RX Datapath BYPASS
