IDDR Modes

Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)

Document ID
AM010
Release Date
2024-03-18
Revision
1.5 English
AMD Versal™ devices have dedicated registers in the IOL to implement input DDR registers. This feature is used by instantiating the IDDRE1 primitive. The IDDRE1 primitive supports the following modes of operation:
OPPOSITE_EDGE
Traditional input DDR solution. Data is presented to Q1 on the rising edge and Q2 on the falling edge.
SAME_EDGE
Data is presented to the device logic on the same clock edge.
SAME_EDGE_PIPELINED
Data is presented to the device logic on the same clock edge. Removes the separated effect but incurs clock latency.

The SAME_EDGE and SAME_EDGE_PIPELINED modes allow designers to transfer falling edge data to the rising edge domain within the IOL, saving configurable logic block (CLB) and clock resources and increasing performance. These modes are implemented using the DDR_CLK_EDGE attribute. The following sections describe each of the operation modes in detail.

OPPOSITE_EDGE mode, a traditional input DDR solution, is accomplished using a single input in the XIOL block. The data is presented to the device logic though the output Q1 on the rising edge of the clock and the output Q2 on the falling edge of the clock. This structure is similar to the previous FPGA implementation. The following timing diagram shows the input DDR using the OPPOSITE_EDGE mode.

Figure 1. OPPOSITE_EDGE Mode


In SAME_EDGE mode, the data is presented into the device logic on the same clock edge. The following timing diagram shows the input DDR using the SAME_EDGE mode. In the timing diagram, the output pairs Q1 and Q2 are no longer (0) and (1). Instead, the first pair presented is pair Q1 (0) and Q2 (don’t care), followed by pair (1) and (2) on the next clock cycle

Figure 2. SAME_EDGE Mode

In SAME_EDGE_PIPELINED mode, the data is presented into the device logic on the same clock edge. Unlike the SAME_EDGE mode, the data pair is not separated by one clock cycle. However, additional clock latency is required to remove the separated effect of the SAME_EDGE mode. The following timing diagram shows the input DDR using the SAME_EDGE_PIPELINED mode. The output pairs Q1 and Q2 are presented to the device logic at the same time.

Figure 3. SAME_EDGE_PIPELINED Mode