Single Data Rate Flip-Flop Primitives

Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)

Document ID
AM010
Release Date
2024-03-18
Revision
1.5 English

SDR input and output registering inside the IOL use a flip-flop primitive in with the IOB = TRUE constraint applied to the flip-flop instance.

Figure 1. Single Data Rate Flip-Flop Primitives

Table 1. Single Data Rate Flip-Flop (FDCE, FDPE, FDRE, FDSE) Attributes
Attribute Values Description
INIT 1'b0, 1'b1 Defines the initial value of the flip-flop
Table 2. Single Data Rate Flip-Flop (FDCE, FDPE, FDRE, FDSE) Ports
Port I/O Description
Q Output Data output
C Input Clock input pin
CE Input Active-High clock enable register
D Input Data input
CLR Input Asynchronous clear (FDCE only)
PRE Input Asynchronous preset (FDPE only)
R Input Synchronous reset (FDRE only)
S Input Synchronous set (FDSE only)