The following table summarizes the key differences between the AMD UltraScale™ architecture PHY and the AMD Versal™ architecture XPHY.
| Function | Versal Architecture XPHY | UltraScale Architecture PHY |
|---|---|---|
| NIBBLESLICEs per nibble | 6 | 6 or 7 |
| Nibbles per bank | 9 (54 pins) | 8 (52 pins) |
| Serialization | 8:1, 4:1, 2:1 | 8:1, 4:1 |
| Deserialization | 1:8, 1:4, 1:2 | 1:8, 1:4 |
| Wizard required to access interface | Yes | No |
| Input and output delays | 625 ps (512 taps) |
UltraScale devices: 1250 ps (512
taps) AMD UltraScale+™ devices: 1100 ps (512 taps) |
Some of the other differences between the PHY architectures of AMD UltraScale™ and Versal devices include the following:
- Receive FIFO bypass support for low-latency applications
- No NIBBLESLICE 0 (formerly called BITSLICE 0) instantiation requirements
- The IDELAYCTRL, ISERDES, OSERDES, RXTX_BITSLICE, RX_BITSLICE, TX_BITSLICE, BITSLICE_CONTROL, and RIU_OR UNISIM primitives are not supported
- The XP IOL resources are independent of the XPHY. Only one or the other can be used at a time.
- Programmable logic control ports are shared between input and output delays through a delay select port
- Some XPIO banks (typically located on the corner of the device) have pins that have limited function and can only be used for DDR memory controller functionality. See the Versal Adaptive SoC Packaging and Pinouts Architecture Manual (AM013) for specific pin information. Also see the Versal Architecture and Product Data Sheet: Overview (DS950).
- QBC and DBC functionality has been split into two parts: Strobes now enter on XCC pins, while inter-nibble and inter-byte clocking capabilities are determined by the nibble.
- The PHY can only be constructed by using the Advanced IO Wizard together with the Advanced I/O Planner (see Advanced I/O Wizard LogiCORE IP Product Guide (PG320)).