25 MHz I/O Clock Range

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

For all frequencies 25 MHz and less, the SD controller uses the clock from the DIV_CLK module.

The clock structure is shown in the Clock Block Diagram. The frequency control is explained in Clock Frequency Divider Register Settings.

RX Interface

The RX interface is clocked by a signal that is looped back from the SCLK output pad. The SCLK output is driven by the DIV_CLK.

TX Interface

The TX interface is clocked by the DIV_CLK and the 10-bit counter driven by the SDx_REF_CLK from the PMC clock controller.