The 4 GB address map includes the
first 2 GBs of DDR memory and 2 GBs for register modules, local memories, and
miscellaneous access ports for the PMC and PSX units. The map also includes small
address window interfaces directly from the PS to the programmable logic (PL) and
address space destinations in the cache coherent PCIe module (CPM), when present.
The following table is organized by destination name.
Destination | Type | Address Range | Size (KB) | Feature | Description | |
---|---|---|---|---|---|---|
Start | End | |||||
APU_DUAL_CSR | reg | 0xFD5C_0000 | 0xFD5C_FFFF | 64 KB | Std | APU control and status |
APU_GIC_CPUIF | local | 0xF904_0000 | 0xF904_FFFF | 64 KB | Std | APU GIC CPU Interface |
APU_GIC_DIST_MAIN | local | 0xF900_0000 | 0xF900_FFFF | 64 KB | Std | APU general interrupt register modules, GIC-500, PL390, local access |
APU_GIC_DIST_MBSPI | local | 0xF901_0000 | 0xF901_FFFF | 64 KB | Std | APU GIC SPI Interrupt Distributor |
APU_GIC_ITS_CTL | local | 0xF902_0000 | 0xF902_FFFF | 64 KB | Std | APU GIC ITS control |
APU_GIC_ITS_TRANS | local | 0xF903_0000 | 0xF903_FFFF | 64 KB | Std | APU GIC ITS service (translator) accessed only by CPM |
APU_GIC_REDIST_CTLLPI_0 | local | 0xF908_0000 | 0xF908_FFFF | 64 KB | Std | APU 0 GIC Redistributor control and Physical LPI |
APU_GIC_REDIST_CTLLPI_1 | local | 0xF90A_0000 | 0xF90A_FFFF | 64 KB | Std | APU 1 GIC Redistributor control and Physical LPI |
APU_GIC_REDIST_SGISPI_0 | local | 0xF909_0000 | 0xF909_FFFF | 64 KB | Std | APU 0 GIC Redistributor for SGI and PPI |
APU_GIC_REDIST_SGISPI_1 | local | 0xF90B_0000 | 0xF90B_FFFF | 64 KB | Std | APU 1 GIC Redistributor for SGI and PPI |
APU_GIC_VCPUIF | local | 0xF906_0000 | 0xF906_FFFF | 64 KB | Std | APU GIC CPU Virtual Interface |
APU_GIC_VIFCTL | local | 0xF905_0000 | 0xF905_FFFF | 64 KB | Std | APU GIC CPU Virtual Interface Control |
CANFD0 | reg | 0xFF06_0000 | 0xFF06_FFFF | 64 KB | Std | Controller Area Network 0 |
CANFD1 | reg | 0xFF07_0000 | 0xFF07_FFFF | 64 KB | Std | Controller Area Network 1 |
CFRAME00_CSR | reg | 0xF12D_0000 | 0xF12D_0FFF | 4 KB | Std | CFU frame 0 control and status |
CFRAME00_FDRI | port | 0xF12D_1000 | 0xF12D_1FFF | 4 KB | Std | CFU frame 0 data register input (FDRI) |
CFRAME01_CSR | reg | 0xF12D_2000 | 0xF12D_2FFF | 4 KB | Std | CFU frame 1 control and status |
CFRAME01_FDRI | port | 0xF12D_3000 | 0xF12D_3FFF | 4 KB | Std | CFU frame 1 data register input (FDRI) |
CFRAME02_CSR | reg | 0xF12D_4000 | 0xF12D_4FFF | 4 KB | Std | CFU frame 2 control and status |
CFRAME02_FDRI | port | 0xF12D_5000 | 0xF12D_5FFF | 4 KB | Std | CFU frame 2 data register input (FDRI) |
CFRAME03_CSR | reg | 0xF12D_6000 | 0xF12D_6FFF | 4 KB | Std | CFU frame 3 control and status |
CFRAME03_FDRI | port | 0xF12D_7000 | 0xF12D_7FFF | 4 KB | Std | CFU frame 3 data register input (FDRI) |
CFRAME04_CSR | reg | 0xF12D_8000 | 0xF12D_8FFF | 4 KB | Std | CFU frame 4 control and status |
CFRAME04_FDRI | port | 0xF12D_9000 | 0xF12D_9FFF | 4 KB | Std | CFU frame 4 data register input (FDRI) |
CFRAME05_CSR | reg | 0xF12D_A000 | 0xF12D_AFFF | 4 KB | Std | CFU frame 5 control and status |
CFRAME05_FDRI | port | 0xF12D_B000 | 0xF12D_BFFF | 4 KB | Std | CFU frame 5 data register input (FDRI) |
CFRAME06_CSR | reg | 0xF12D_C000 | 0xF12D_CFFF | 4 KB | Std | CFU frame 6 control and status |
CFRAME06_FDRI | port | 0xF12D_D000 | 0xF12D_DFFF | 4 KB | Std | CFU frame 6 data register input (FDRI) |
CFRAME07_CSR | reg | 0xF12D_E000 | 0xF12D_EFFF | 4 KB | Std | CFU frame 7 control and status |
CFRAME07_FDRI | port | 0xF12D_F000 | 0xF12D_FFFF | 4 KB | Std | CFU frame 7 data register input (FDRI) |
CFRAME08_CSR | reg | 0xF12E_0000 | 0xF12E_0FFF | 4 KB | Std | CFU frame 8 control and status |
CFRAME08_FDRI | port | 0xF12E_1000 | 0xF12E_1FFF | 4 KB | Std | CFU frame 8 data register input (FDRI) |
CFRAME09_CSR | reg | 0xF12E_2000 | 0xF12E_2FFF | 4 KB | Std | CFU frame 9 control and status |
CFRAME09_FDRI | port | 0xF12E_3000 | 0xF12E_3FFF | 4 KB | Std | CFU frame 9 data register input (FDRI) |
CFRAME10_CSR | reg | 0xF12E_4000 | 0xF12E_4FFF | 4 KB | Std | CFU frame 10 control and status |
CFRAME10_FDRI | port | 0xF12E_5000 | 0xF12E_5FFF | 4 KB | Std | CFU frame 10 data register input (FDRI) |
CFRAME11_CSR | reg | 0xF12E_6000 | 0xF12E_6FFF | 4 KB | Std | CFU frame 11 control and status |
CFRAME11_FDRI | port | 0xF12E_7000 | 0xF12E_7FFF | 4 KB | Std | CFU frame 11 data register input (FDRI) |
CFRAME12_CSR | reg | 0xF12E_8000 | 0xF12E_8FFF | 4 KB | Std | CFU frame 12 control and status |
CFRAME12_FDRI | port | 0xF12E_9000 | 0xF12E_9FFF | 4 KB | Std | CFU frame 12 data register input (FDRI) |
CFRAME13_CSR | reg | 0xF12E_A000 | 0xF12E_AFFF | 4 KB | Std | CFU frame 13 control and status |
CFRAME13_FDRI | port | 0xF12E_B000 | 0xF12E_BFFF | 4 KB | Std | CFU frame 13 data register input (FDRI) |
CFRAME14_CSR | reg | 0xF12E_C000 | 0xF12E_CFFF | 4 KB | Std | CFU frame 14 control and status |
CFRAME14_FDRI | port | 0xF12E_D000 | 0xF12E_DFFF | 4 KB | Std | CFU frame 14 data register input (FDRI) |
CFRAME_BCAST_CSR | reg | 0xF12E_E000 | 0xF12E_EFFF | 4 KB | Std | CFU frame broadcast control and status |
CFRAME_BCAST_FDRI | port | 0xF12E_F000 | 0xF12E_FFFF | 4 KB | Std | CFU frame broadcast data register input (FDRI) |
CFU_CSR | reg | 0xF12B_0000 | 0xF12B_FFFF | 64 KB | Std | Configuration Frame Unit (CFU) control and status |
CFU_FDRO_mmap | port | 0xF12C_2000 | 0xF12C_2FFF | 4 KB | Std | CFU frame data register output (FDRO) |
CFU_SFR_mem | mem | 0xF12C_1000 | 0xF12C_1FFF | 4 KB | Std | CFU single frame read register |
CFU_STREAM_port | port | 0xF1F8_0000 | 0xF1FB_FFFF | 256 KB | Std | CFU Stream |
CPM4_ADDRREMAP | reg | 0xFCF3_0000 | 0xFCF3_FFFF | 64 KB | Opt | CPM4 Re-map Control |
CPM4_CMN | reg | 0xFC00_0000 | 0xFC9F_FFFF | 10 MB | CPM4 | CPM4 CMN Registers |
CPM4_CRX | reg | 0xFCA0_0000 | 0xFCBF_FFFF | 64 KB | Opt | CPM4 Clock and Reset Controllers |
CPM4_CSR | reg | 0xFCFF_0000 | 0xFCFF_FFFF | 64 KB | Opt | CPM control and status |
CPM4_DMA_ATTR | reg | 0xFCA7_0000 | 0xFCA7_FFFF | 64 KB | Opt | CPM4 PCIe DMA Attributes (program with design tools) |
CPM4_DVSEC_0 | reg | 0xFCFB_0000 | 0xFCFB_FFFF | 64 KB | Opt | CPM4 DVSEC 0 Buffer |
CPM4_DVSEC_1 | reg | 0xFCFC_0000 | 0xFCFC_FFFF | 64 KB | Opt | CPM4 DVSEC 1 Buffer |
CPM4_INT_CSR | reg | 0xFCB4_0000 | 0xFCB0_FFFF | 1.5 MB | Opt | CPM4 Interconnect Contrl and Status |
CPM4_INT_GPV | reg | 0xFCB0_0000 | 0xFCB0_FFFF | 128 KB | Opt | CPM4 Interconnect Global Programming View (GPV) |
CPM4_L2_CSR | reg | 0xFCD0_0000 | 0xFCD7_FFFF | 512 KB | Opt | CPM2 L2 Cache Control and Status (aka CPM_L2_0_CONFIG) |
CPM4_PCIE0_ATTR | reg | 0xFCA5_0000 | 0xFCA5_FFFF | 64 KB | Opt | CPM4 PCIe0 Attributes (program with design tools) |
CPM4_PCIE1_ATTR | reg | 0xFCA6_0000 | 0xFCA6_FFFF | 64 KB | Opt | CPM4 PCIe1 Attributes (program with design tools) |
CPM4_PCIe0_mem | mem | 0xE000_0000 | 0xEFFF_FFFF | 256 MB | CPM4 | PCIe Region 0 in CPM4 |
CPM4_PCIe_DMA | reg | 0xFCFE_0000 | 0xFCFE_FFFF | 64 KB | Opt | CPM DMA control and status |
CPM4_SLCR | reg | 0xFCA1_0000 | 0xFCA1_FFFF | 64 KB | Opt | CPM4 System-level Control and Status |
CPM4_SLCR_SECURE | reg | 0xFCA2_0000 | 0xFCA2_FFFF | 64 KB | Opt | CPM4 System-level Control and Status (secure) |
CPM4_XDMA_CSR | reg | 0xE100_0000 | 0xE100_FFFF | 64 KB | CPM4 | CPM4 DMA control registers (XDMA) |
CPM5_ADDRREMAP | reg | 0xFCDB_0000 | 0xFCDB_FFFF | 64 KB | CPM5 | CPM5 Address ReMap control |
CPM5_CMN | reg | 0xFC00_0000 | 0xFC9F_FFFF | 10 MB | CPM5 | CPM5 Cache Mesh Network Registers |
CPM5_CRX | reg | 0xFCDC_0000 | 0xFCDC_FFFF | 64 KB | CPM5 | CPM5 Clock and Reset registers |
CPM5_CRX | reg | 0xFCA0_0000 | 0xFCBF_FFFF | 2 MB | CPM5 | CPM5 Clock and Reset Registers |
CPM5_DMA0_ATTR | reg | 0xFCE1_0000 | 0xFCE1_FFFF | 64 KB | CPM5 | CPM5 DMA Controller 0 Attributes |
CPM5_DMA0_CSR | reg | 0xFCE2_0000 | 0xFCE2_FFFF | 64 KB | CPM5 | CPM5 DMA Controller 0 Control and Status |
CPM5_DMA1_ATTR | reg | 0xFCE9_0000 | 0xFCE9_FFFF | 64 KB | CPM5 | CPM5 DMA Controller 1 Attributes |
CPM5_DMA1_CSR | reg | 0xFCEA_0000 | 0xFCEA_FFFF | 64 KB | CPM5 | CPM5 DMA Controller 1 Control and Status |
CPM5_DPLL0_ATTR | reg | 0xFCE3_0000 | 0xFCE3_FFFF | 64 KB | CPM5 | CPM5 Digital PLL 0 Control |
CPM5_DPLL1_ATTR | reg | 0xFCEB_0000 | 0xFCEB_FFFF | 64 KB | CPM5 | CPM5 Digital PLL 1 Control |
CPM5_DVSEC0 | reg | 0xFCE4_0000 | 0xFCE4_FFFF | 64 KB | CPM5 | CPM5 Device Security Controller 0 |
CPM5_DVSEC1 | reg | 0xFCEC_0000 | 0xFCEC_FFFF | 64 KB | CPM5 | CPM5 Device Security Controller 1 |
CPM5_INT_GPV | reg | 0xFCD8_0000 | 0xFCD9_FFFF | 128 | CPM5 | CPM5 Global Programmer's View Interconnect control |
CPM5_L20_CSR | reg | 0xFCC0_0000 | 0xFCC7_FFFF | 512 KB | CPM5 | CPM5 L2 Cache 0 Control and Status |
CPM5_L21_CSR | reg | 0xFCC8_0000 | 0xFCCF_FFFF | 512 KB | CPM5 | CPM5 L2 Cache 1 Control and Status |
CPM5_PCIE0_ATTR | reg | 0xFCE0_8000 | 0xFCE0_FFFF | 32 KB | CPM5 | CPM5 PCIe Controller 0 Attributes |
CPM5_PCIE0_CSR | reg | 0xFCE0_0000 | 0xFCE0_7FFF | 32 KB | CPM5 | CPM5 PCIe Controller 0 Control and Status |
CPM5_PCIE1_ATTR | reg | 0xFCE8_8000 | 0xFCE8_FFFF | 32 KB | CPM5 | CPM5 PCIe Controller 1 Attributes |
CPM5_PCIE1_CSR | reg | 0xFCE8_0000 | 0xFCE8_7FFF | 32 KB | CPM5 | CPM5 PCIe Controller 1 Control and Status |
CPM5_PCIe0_mem | mem | 0xE000_0000 | 0xEFFF_FFFF | 256 MB | CPM5 | CPM5 Interconnect to CPM5 APB switch |
CPM5_PCSR | reg | 0xFCFF_0000 | 0xFCFF_FFFF | 64 KB | CPM5 | CPM5 Control and Status Registers |
CPM5_SLCR | reg | 0xFCDD_0000 | 0xFCDD_FFFF | 64 KB | CPM5 | CPM5 System-level Control Registers |
CPM5_SLCR_SECURE | reg | 0xFCDE_0000 | 0xFCDE_FFFF | 64 KB | CPM5 | CPM5 Secure System-level Control Registers |
CRF | reg | 0xFD1A_0000 | 0xFD2D_FFFF | 1.25 MB | Std | FPD Clock and Reset controller |
CRL | reg | 0xFF5E_0000 | 0xFF8D_FFFF | 3 MB | Std | LPD Clock and Reset controller |
CRP | reg | 0xF126_0000 | 0xF126_FFFF | 64 KB | Std | PMC Clock and Reset control |
DBG_APU0_CTI | reg | 0xF0D1_0000 | 0xF0D1_FFFF | 64 KB | Std | CoreSight APU0 Map Trigger and Channel interfaces |
DBG_APU0_DBG | reg | 0xF0D0_0000 | 0xF0D0_FFFF | 64 KB | Std | CoreSight APU0 Built-in Debug Logic |
DBG_APU0_ETM | reg | 0xF0D3_0000 | 0xF0D3_FFFF | 64 KB | Std | CoreSight APU0 Generate Trace |
DBG_APU0_PMU | reg | 0xF0D2_0000 | 0xF0D2_FFFF | 64 KB | Std | CoreSight APU0 Processor Performance Profile |
DBG_APU1_CTI | reg | 0xF0D5_0000 | 0xF0D5_FFFF | 64 KB | Std | CoreSight APU1 Map Trigger and Channel interfaces |
DBG_APU1_DBG | reg | 0xF0D4_0000 | 0xF0D4_FFFF | 64 KB | Std | CoreSight APU1 Built-in Debug Logic |
DBG_APU1_ETM | reg | 0xF0D7_0000 | 0xF0D7_FFFF | 64 KB | Std | CoreSight APU1 Generate Trace |
DBG_APU1_PMU | reg | 0xF0D6_0000 | 0xF0D6_FFFF | 64 KB | Std | CoreSight APU1 Processor Performance Profile |
DBG_APU_CTI | reg | 0xF0CA_0000 | 0xF0CA_FFFF | 64 KB | Std | CoreSight APU MPCore Map Trigger and Channel |
DBG_APU_ELA | reg | 0xF0C6_0000 | 0xF0C6_FFFF | 64 KB | Std | CoreSight APU Embedded 128 Logic Analyzer |
DBG_APU_ETF | reg | 0xF0C3_0000 | 0xF0C3_FFFF | 64 KB | Std | CoreSight APU Embedded 4K Trace FIFO |
DBG_APU_FUN | reg | 0xF0C2_0000 | 0xF0C2_FFFF | 64 KB | Std | CoreSight APU Merge Two Trace Streams to ATB |
DBG_CPM_CTI2A | reg | 0xF0FA_0000 | 0xF0FA_FFFF | 64 KB | Std | CoreSight CPM 2A Map Trigger and Channel interfaces |
DBG_CPM_CTI2D | reg | 0xF0FD_0000 | 0xF0FD_FFFF | 64 KB | Std | CoreSight CPM 2D Map Trigger and Channel interfaces |
DBG_CPM_ELA2A | reg | 0xF0F4_0000 | 0xF0F4_FFFF | 64 KB | Std | CoreSight CPM 2A Embedded 256 Logic Analyzer |
DBG_CPM_ELA2B | reg | 0xF0F5_0000 | 0xF0F5_FFFF | 64 KB | Std | CoreSight CPM 2B Embedded 256 Logic Analyzer |
DBG_CPM_ELA2C | reg | 0xF0F6_0000 | 0xF0F6_FFFF | 64 KB | Std | CoreSight CPM 2C Embedded 256 Logic Analyzer |
DBG_CPM_ELA2D | reg | 0xF0F7_0000 | 0xF0F7_FFFF | 64 KB | Std | CoreSight CPM 2D Embedded 256 Logic Analyzer |
DBG_CPM_FUN | reg | 0xF0F2_0000 | 0xF0F2_FFFF | 64 KB | Std | CoreSight CPM Merge Two Trace Streams to ATB |
DBG_CPM_ROM | reg | 0xF0F0_0000 | 0xF0F0_FFFF | 64 KB | Std | CoreSight CPM ROM |
DBG_FPD_CTI1B | reg | 0xF0BB_0000 | 0xF0BB_FFFF | 64 KB | Std | CoreSight FPD 1B Map Trigger and Channel interfaces |
DBG_FPD_CTI1C | reg | 0xF0BC_0000 | 0xF0BC_FFFF | 64 KB | Std | CoreSight FPD 1C Map Trigger and Channel interfaces |
DBG_FPD_CTI1D | reg | 0xF0BD_0000 | 0xF0BD_FFFF | 64 KB | Std | CoreSight FPD 1D Map Trigger and Channel interfaces |
DBG_FPD_ETF | reg | 0xF0B3_0000 | 0xF0B3_FFFF | 64 KB | Std | CoreSight FPD Embedded 32K Trace FIFO |
DBG_FPD_ETR | reg | 0xF0B5_0000 | 0xF0B5_FFFF | 64 KB | Std | CoreSight FPD Enable Local Trace Buffer |
DBG_FPD_FUN | reg | 0xF0B2_0000 | 0xF0B2_FFFF | 64 KB | Std | CoreSight LPD Merge Six Trace Streams to ATB |
DBG_FPD_GPR | reg | 0xF0B1_0000 | 0xF0B1_FFFF | 64 KB | Std | CoreSight FPD GPR 2P |
DBG_FPD_REPL | reg | 0xF0B4_0000 | 0xF0B4_FFFF | 64 KB | Std | CoreSight Replicates ATB Data Stream |
DBG_FPD_ROM | reg | 0xF0B0_0000 | 0xF0B0_FFFF | 64 KB | Std | CoreSight FPD ROM |
DBG_LPD_CTI | reg | 0xF09D_0000 | 0xF09D_FFFF | 64 KB | Std | CoreSight LPD Map Trigger and Channel interfaces |
DBG_LPD_FUN | reg | 0xF092_0000 | 0xF092_FFFF | 64 KB | Std | CoreSight LPD Merge Five Trace Streams to ATB |
DBG_LPD_GPR | reg | 0xF091_0000 | 0xF091_FFFF | 64 KB | Std | CoreSight LPD GPR 3P |
DBG_LPD_ROM | reg | 0xF090_0000 | 0xF090_FFFF | 64 KB | Std | CoreSight LPD ROM |
DBG_PMC_CTI | reg | 0xF08D_0000 | 0xF08D_FFFF | 64 KB | Std | CoreSight PMC Map Trigger and Channel interfaces |
DBG_PMC_GPR | reg | 0xF081_0000 | 0xF081_FFFF | 64 KB | Std | CoreSight PMC GPR 1P |
DBG_PMC_ROM | reg | 0xF080_0000 | 0xF080_FFFF | 64 KB | Std | CoreSight PMC ROM |
DBG_RPU0_CTI | reg | 0xF0A1_0000 | 0xF0A1_FFFF | 64 KB | Std | CoreSight RPU0 Map Trigger and Channel interfaces |
DBG_RPU0_DBG | reg | 0xF0A0_0000 | 0xF0A0_FFFF | 64 KB | Std | CoreSight RPU0 Built-in Debug Logic |
DBG_RPU0_ETM | reg | 0xF0A3_0000 | 0xF0A3_FFFF | 64 KB | Std | CoreSight RPU 0 Generate Trace |
DBG_RPU1_CTI | reg | 0xF0A5_0000 | 0xF0A5_FFFF | 64 KB | Std | CoreSight RPU1 Map Trigger and Channel interfaces |
DBG_RPU1_DBG | reg | 0xF0A4_0000 | 0xF0A4_FFFF | 64 KB | Std | CoreSight RPU1 Built-in Debug Logic |
DBG_RPU1_ETM | reg | 0xF0A7_0000 | 0xF0A7_FFFF | 64 KB | Std | CoreSight RPU1 Generate Trace |
DBG_STM | reg | 0xF0B7_0000 | 0xF0B7_FFFF | 64 KB | Std | CoreSight System Trace Module |
DBG_STM_mem | mem | 0xF800_0000 | 0xF8FF_FFFF | 16 MB | Std | Debug System Trace Macrocell |
DBG_TPIU | reg | 0xF0B6_0000 | 0xF0B6_FFFF | 64 KB | Std | CoreSight Test port interface unit |
DBG_TSG_RW | reg | 0xF099_0000 | 0xF099_FFFF | 64 KB | Std | CoreSight Master Time Stamp with Read/Write |
DDRMC0_region0_mem | mem | 0x0000_0000 | 0x7FFF_FFFF | 2 GB | Std | DRAM Memory Controller 0, Region 0 (lower 2GB) |
DPC_AURORA | reg | 0xFF9C_0000 | 0xFF9C_FFFF | 64 KB | Std | Aurora Debug Interface (aka HSDP_AURORA) |
DPC_DMA_CSR | reg | 0xFE5F_0000 | 0xFE5F_FFFF | 64 KB | Std | Debug Port Controller DMA unit |
FPD_AXI_PL_mmap | mmap | 0xA400_0000 | 0xAFFF_FFFF | 192 MB | Std | PS-to-PL AXI Interface from FPD, lower |
FPD_AXI_PL_mmap | mmap | 0xB000_0000 | 0xBFFF_FFFF | 256 MB | Std | PS-to-PL AXI Interface from FPD, upper |
FPD_CCI_CORE | reg | 0xFD00_0000 | 0xFD0F_FFFF | 1 MB | Std | Cache Coherent Interconnect (CCI-500) in FPD |
FPD_CCI_CSR | reg | 0xFD5E_0000 | 0xFD5E_FFFF | 64 KB | Std | Cache Coherent Interconnect (aka CCI_REG) |
FPD_INT_CSR | reg | 0xFD37_0000 | 0xFD37_FFFF | 64 KB | Std | FPD Interconnect control, wrapper |
FPD_INT_GPV | reg | 0xFD70_0000 | 0xFD7F_FFFF | 1 MB | Std | FPD Interconnect Global Programmers View (GPV) |
FPD_SLCR | reg | 0xFD61_0000 | 0xFD61_FFFF | 64 KB | Std | FPD System-level Control |
FPD_SLCR_SECURE | reg | 0xFD69_0000 | 0xFD69_FFFF | 64 KB | Std | FPD System-level Control (secure) |
FPD_SMMU | reg | 0xFD80_0000 | 0xFDFF_FFFF | 8 MB | Std | SMMU core (non-secure 8 MB space) |
FPD_SMMU_CSR | reg | 0xFD5F_0000 | 0xFD5F_FFFF | 64 KB | Std | System Memory Management Unit |
FPD_SMMU_SECURE | reg | 0xFD80_0000 | 0xFDFF_FFFF | 8 MB | Std | SMMU core (secure 8 MB space) |
FPD_SWDT | reg | 0xFD4D_0000 | 0xFD4D_FFFF | 64 KB | Std | FPD System Watchdog Timer (aka SWDT1, WWDT1)) |
FPD_XMPU | reg | 0xFD39_0000 | 0xFD39_FFFF | 64 KB | Std | FPD Memory Protection Unit |
GEM0 | reg | 0xFF0C_0000 | 0xFF0C_FFFF | 64 KB | Std | Gigabit Ethernet MAC (GEM) controller 0 |
GEM1 | reg | 0xFF0D_0000 | 0xFF0D_FFFF | 64 KB | Std | Gigabit Ethernet MAC (GEM) controller 1 |
IPI | reg | 0xFF30_0000 | 0xFF3F_FFFF | 1 MB | Std | Inter-processor Interrupts |
LPD_AXI_PL_mmap | mmap | 0x8000_0000 | 0x9FFF_FFFF | 512 MB | Std | PS-to-PL AXI Interface from LPD |
LPD_DMA_CH0 | reg | 0xFFA8_0000 | 0xFFA8_FFFF | 64 KB | Std | General purpose DMA channel 0 (aka ADMA) |
LPD_DMA_CH1 | reg | 0xFFA9_0000 | 0xFFA9_FFFF | 64 KB | Std | General purpose DMA channel 1 |
LPD_DMA_CH2 | reg | 0xFFAA_0000 | 0xFFAA_FFFF | 64 KB | Std | General purpose DMA channel 2 |
LPD_DMA_CH3 | reg | 0xFFAB_0000 | 0xFFAB_FFFF | 64 KB | Std | General purpose DMA channel 3 |
LPD_DMA_CH4 | reg | 0xFFAC_0000 | 0xFFAC_FFFF | 64 KB | Std | General purpose DMA channel 4 |
LPD_DMA_CH5 | reg | 0xFFAD_0000 | 0xFFAD_FFFF | 64 KB | Std | General purpose DMA channel 5 |
LPD_DMA_CH6 | reg | 0xFFAE_0000 | 0xFFAE_FFFF | 64 KB | Std | General purpose DMA channel 6 |
LPD_DMA_CH7 | reg | 0xFFAF_0000 | 0xFFAF_FFFF | 64 KB | Std | General purpose DMA channel 7 |
LPD_GPIO | reg | 0xFF0B_0000 | 0xFF0B_FFFF | 64 KB | Std | LPD General Purpose I/O |
LPD_I2C0 | reg | 0xFF02_0000 | 0xFF02_FFFF | 64 KB | Std | Inter-integrated Circuit controller 0 |
LPD_I2C1 | reg | 0xFF03_0000 | 0xFF03_FFFF | 64 KB | Std | Inter-integrated Circuit controller 1 |
LPD_INT_CSR | reg | 0xFE60_0000 | 0xFE7F_FFFF | 2 MB | Std | LPD Interconnect Timeout, Reset, and Isolation |
LPD_INT_GPV | reg | 0xFE40_0000 | 0xFE41_FFFF | 128 KB | Std | LPD Interconnect Global Programmers View (GPV) |
LPD_IOP_INT_GPV | reg | 0xFE00_0000 | 0xFE0F_FFFF | 1 MB | Std | LPD IOP Interconnect Global Programmers View (GPV) |
LPD_IOP_SLCR | reg | 0xFF08_0000 | 0xFF09_FFFF | 128 KB | Std | LPD IOP System-level Control |
LPD_IOP_SLCR_SECURE | reg | 0xFF0A_0000 | 0xFF0A_FFFF | 64 KB | Std | LPD IOP System-level Control, secure |
LPD_SLCR | reg | 0xFF41_0000 | 0xFF50_FFFF | 1 MB | Std | LPD System-level control |
LPD_SLCR_SECURE | reg | 0xFF51_0000 | 0xFF54_FFFF | 256 KB | Std | LPD System-level control, secure |
LPD_SWDT | reg | 0xFF12_0000 | 0xFF12_FFFF | 64 KB | Std | LPD System Watchdog Timer (aka SWDT0, WWDT0) |
LPD_XPPU | reg | 0xFF99_0000 | 0xFF99_FFFF | 64 KB | Std | LPD Peripheral Protection control |
NPI_HOST_mem | mem | 0xF600_0000 | 0xF7FF_FFFF | 32 MB | Std | NPI Host controller memory space |
OCM_CSR | reg | 0xFF96_0000 | 0xFF96_FFFF | 64 KB | Std | On-chip Memory control |
OCM_XMPU | reg | 0xFF98_0000 | 0xFF98_FFFF | 64 KB | Std | OCM Memory Protection control |
OCM_mem | mem | 0xFFFC_0000 | 0xFFFF_FFFF | 256 KB | Std | On-chip Memory space |
OSPI | reg | 0xF101_0000 | 0xF101_FFFF | 64 KB | Std | Octal-SPI control |
OSPI_mem | mem | 0xC000_0000 | 0xDFFF_FFFF | 512 MB | Std | Octal-SPI Linear Mode memory space |
PLM_RTCA | mreg | 0xF201_4000 | 0xF201_4FFF | 4 KB | Std | Real-time Configuration Area - Note: Fixed location in PMC RAM |
PL_ACELITE_FPD_CSR | reg | 0xFD38_0000 | 0xFD38_FFFF | 64 KB | Std | PL to PS Coherent AXI control (aka S_AXI_HPC, AFIFM2) |
PL_AXI_FPD_CSR | reg | 0xFD36_0000 | 0xFD36_FFFF | 64 KB | Std | PL to PS AXI Interface control (aka S_AXI_HP, AFIFM0) |
PL_AXI_LPD_CSR | reg | 0xFF9B_0000 | 0xFF9B_FFFF | 64 KB | Std | PL to PS 128-bit AXI Channel (aka AFIFM4) |
PMC_AES | reg | 0xF11E_0000 | 0xF11E_FFFF | 64 KB | Std | AES Module (controlled under NDA) |
PMC_ANLG | reg | 0xF116_0000 | 0xF119_FFFF | 256 KB | Std | PMC analog voltage monitoring control |
PMC_BBRAM_CTRL | reg | 0xF11F_0000 | 0xF11F_FFFF | 64 KB | Std | Batter-backed RAM, BBRAM (controlled under NDA) |
PMC_DMA0_CSR | reg | 0xF11C_0000 | 0xF11C_FFFF | 64 KB | Std | PMC DMA 0 Control |
PMC_DMA1_CSR | reg | 0xF11D_0000 | 0xF11D_FFFF | 64 KB | Std | PMC DMA 1 Control |
PMC_ECDSA_RSA | reg | 0xF120_0000 | 0xF120_FFFF | 64 KB | Std | ECDSA and RSA control (controlled under NDA) |
PMC_EFUSE_CACHE | reg | 0xF125_0000 | 0xF125_FFFF | 64 KB | Std | eFuse Cache (mostly controlled under NDA) |
PMC_EFUSE_CTRL | reg | 0xF124_0000 | 0xF124_FFFF | 64 KB | Std | eFuse Control Unit (partially controlled under NDA) |
PMC_GLOBAL | reg | 0xF111_0000 | 0xF115_FFFF | 320 KB | Std | PMC Global registers |
PMC_GPIO | reg | 0xF102_0000 | 0xF102_FFFF | 64 KB | Std | General Purpose I/O in PMC |
PMC_I2C | reg | 0xF100_0000 | 0xF100_FFFF | 64 KB | Std | PMC I2C controller |
PMC_INT_CSR | reg | 0xF133_0000 | 0xF15A_FFFF | 2.5 MB | Std | PMC reset and isolation interconnect ports |
PMC_INT_GPV | reg | 0xF132_0000 | 0xF132_FFFF | 64 KB | Std | PMC Interconnect Global Programmers View (GPV) |
PMC_IOP_INT_GPV | reg | 0xF108_0000 | 0xF108_FFFF | 64 KB | Std | PMC IOP Interconnect Global Programmers View (GPV) |
PMC_IOP_SLCR | reg | 0xF106_0000 | 0xF106_FFFF | 64 KB | Std | PMC IOP SLCR registers, non-secure |
PMC_IOP_SLCR_SECURE | reg | 0xF107_0000 | 0xF107_FFFF | 64 KB | Std | PMC IOP SLCR registers, secure |
PMC_JTAG_CSR | reg | 0xF11A_0000 | 0xF11B_FFFF | 128 KB | Std | PMC JTAG TAP control |
PMC_LOCAL | reg | 0xF004_0000 | 0xF004_FFFF | 64 KB | Std | PMC Local registers |
PMC_PUF | reg | 0xF005_0000 | 0xF005_FFFF | 64 KB | Std | PUF control registers |
PMC_RAM_CSR | reg | 0xF110_0000 | 0xF110_FFFF | 64 KB | Std | PMC On-chip Memory configuration |
PMC_RAM_mem | mem | 0xF200_0000 | 0xF201_FFFF | 128 KB | Std | PMC RAM (128 KB) - Note: The usage of this memory is defined by the PLM. |
PMC_RTC | reg | 0xF12A_0000 | 0xF12A_FFFF | 64 KB | Std | RTC Registers |
PMC_SBI_CSR | reg | 0xF122_0000 | 0xF122_FFFF | 64 KB | Std | Boot Interface |
PMC_SBI_STREAM_mem | mem | 0xF210_0000 | 0xF210_FFFF | 64 KB | Std | SBI Stream memory |
PMC_SHA3 | reg | 0xF121_0000 | 0xF121_FFFF | 64 KB | Std | SHA3 Module (controlled under NDA) |
PMC_SYSMON_CSR | reg | 0xF127_0000 | 0xF129_FFFF | 192 KB | Std | PMC System Monitor control |
PMC_TRNG | reg | 0xF123_0000 | 0xF123_FFFF | 64 KB | Std | True Random Number Generator (controlled under NDA) |
PMC_XMPU | reg | 0xF12F_0000 | 0xF12F_FFFF | 64 KB | Std | PMC Memory Protection Unit |
PMC_XPPU | reg | 0xF131_0000 | 0xF131_FFFF | 64 KB | Std | PMC Peripheral Protection Unit |
PMC_XPPU_NPI | reg | 0xF130_0000 | 0xF130_FFFF | 64 KB | Std | NPI Host Memory Protection Unit |
PPU_DCACHE_CTRL | reg | 0xF028_2000 | 0xF028_2FFF | 4 KB | Std | PPU Data Cache ECC control |
PPU_ICACHE_CTRL | reg | 0xF028_1000 | 0xF028_1FFF | 4 KB | Std | PPU Instruction Cache ECC control |
PPU_IOMODULE | reg | 0xF028_0000 | 0xF028_0FFF | 4 KB | Std | PPU I/O Module registers |
PPU_MDM | reg | 0xF031_0000 | 0xF031_7FFF | 32 KB | Std | PPU Debug Module control |
PPU_RAM_DATA_mem | mem | 0xF024_0000 | 0xF025_FFFF | 128 KB | Std | PPU D-cache Addressable |
PPU_RAM_INSTR_mem | mem | 0xF020_0000 | 0xF023_FFFF | 256 KB | Std | PPU I-cache Addressable |
PPU_TMR_INJECT | reg | 0xF028_4000 | 0xF028_4FFF | 4 KB | Std | PPU Triple Redundancy Error Injection |
PPU_TMR_MANAGER | reg | 0xF028_3000 | 0xF028_3FFF | 4 KB | Std | PPU Triple Redundancy Manager |
PPU_TMR_TRACE | reg | 0xF030_0000 | 0xF030_0FFF | 4 KB | Std | PPU Trace |
PSM_DCACHE_ECC | reg | 0xFFCB_0000 | 0xFFCB_FFFF | 64 KB | Std | PSM D-cache ECC control |
PSM_DCACHE_mem | mem | 0xFFC2_0000 | 0xFFC3_FFFF | 128 KB | Std | PSM D-cache Addressable |
PSM_GLOBAL | reg | 0xFFC9_0000 | 0xFFC9_EFFF | 60 KB | Std | PSM Global registers |
PSM_ICACHE_ECC | reg | 0xFFCA_0000 | 0xFFCA_FFFF | 64 KB | Std | PSM I-cache ECC control |
PSM_ICACHE_mem | mem | 0xFFC0_0000 | 0xFFC1_FFFF | 128 KB | Std | PSM I-cache Addressable |
PSM_INT_GPV | reg | 0xFFC9_F000 | 0xFFC9_FFFF | 4 KB | Std | PSM Interconnect Global Programmers View (GPV) |
PSM_IOMODULE | reg | 0xFFC8_0000 | 0xFFC8_7FFF | 32 KB | Std | PSM I/O Module registers |
PSM_LOCAL | reg | 0xFFC8_8000 | 0xFFC8_FFFF | 32 KB | Std | PSM Local registers |
PSM_MDM | reg | 0xFFCF_0000 | 0xFFCF_FFFF | 64 KB | Std | PSM Debug Module control |
PSM_TMR_INJECT | reg | 0xFFCD_0000 | 0xFFCD_FFFF | 64 KB | Std | PSM Triple Redundancy Error Injection |
PSM_TMR_MANAGER | reg | 0xFFCC_0000 | 0xFFCC_FFFF | 64 KB | Std | PSM Triple Redundancy Manager |
PSM_TMR_TRACE | reg | 0xFFCE_0000 | 0xFFCE_FFFF | 64 KB | Std | PSM Trace Module control |
QSPI | reg | 0xF103_0000 | 0xF103_FFFF | 64 KB | Std | Quad-SPI control |
RPU0_DCACHE_mem | mem | 0xFFE5_0000 | 0xFFE5_7FFF | 32 KB | Std | RPU0 data cache lock-step and dual modes |
RPU0_ICACHE_mem | mem | 0xFFE4_0000 | 0xFFE4_7FFF | 32 KB | Std | RPU0 instruction cache lock-step and dual modes |
RPU0_TCMA_mem | mem | 0xFFE0_0000 | 0xFFE0_FFFF | 64 KB | Std | RPU0 TCM A lock-step and dual modes |
RPU0_TCMA_mem_lockstep | mem | 0xFFE1_0000 | 0xFFE1_FFFF | 64 KB | Std | RPU0 TCM A lock-step mode |
RPU0_TCMB_mem | mem | 0xFFE2_0000 | 0xFFE2_FFFF | 64 KB | Std | RPU0 TCM B lock-step and dual modes |
RPU0_TCMB_mem_lockstep | mem | 0xFFE3_0000 | 0xFFE3_FFFF | 64 KB | Std | RPU0 TCM B lock-step mode |
RPU1_DCACHE_mem_dual | mem | 0xFFED_0000 | 0xFFED_7FFF | 32 KB | Std | RPU1 data cache dual mode |
RPU1_ICACHE_mem_dual | mem | 0xFFEC_0000 | 0xFFED_7FFF | 32 KB | Std | RPU1 instruction cache dual mode |
RPU1_TCMA_mem_dual | mem | 0xFFE9_0000 | 0xFFE9_FFFF | 64 KB | Std | RPU1 TCM A dual mode |
RPU1_TCMB_mem_dual | mem | 0xFFEB_0000 | 0xFFEB_FFFF | 64 KB | Std | RPU1 TCM B dual mode |
RPU_DUAL_CSR | reg | 0xFF9A_0000 | 0xFF9A_FFFF | 64 KB | Std | RPU control and status |
RPU_GIC | local | 0xF900_0000 | 0xF900_2FFF | 12 KB | Std | RPU general interrupt register modules, PL390, local access |
SD_eMMC0 | reg | 0xF104_0000 | 0xF104_FFFF | 64 KB | Std | SD/eMMC controller 0 |
SD_eMMC1 | reg | 0xF105_0000 | 0xF105_FFFF | 64 KB | Std | SD/eMMC controller 1 |
SPI0 | reg | 0xFF04_0000 | 0xFF04_FFFF | 64 KB | Std | Serial Peripheral Interface 0 |
SPI1 | reg | 0xFF05_0000 | 0xFF05_FFFF | 64 KB | Std | Serial Peripheral Interface 1 |
SYS_COUNT_CSR | reg | 0xFF14_0000 | 0xFF14_FFFF | 64 KB | Std | System software counter control and status |
SYS_COUNT_READ | reg | 0xFF13_0000 | 0xFF13_FFFF | 64 KB | Std | System software counter read |
TTC0 | reg | 0xFF0E_0000 | 0xFF0E_FFFF | 64 KB | Std | Triple Timer Counter 0 |
TTC1 | reg | 0xFF0F_0000 | 0xFF0F_FFFF | 64 KB | Std | Triple Timer Counter 1 |
TTC2 | reg | 0xFF10_0000 | 0xFF10_FFFF | 64 KB | Std | Triple Timer Counter 2 |
TTC3 | reg | 0xFF11_0000 | 0xFF11_FFFF | 64 KB | Std | Triple Timer Counter 3 |
UART0 | reg | 0xFF00_0000 | 0xFF00_FFFF | 64 KB | Std | UART 0 controller |
UART1 | reg | 0xFF01_0000 | 0xFF01_FFFF | 64 KB | Std | UART 1 controller |
USB_CSR | reg | 0xFF9D_0000 | 0xFF9D_FFFF | 64 KB | Std | USB 2.0 control in LPD |
USB_XHCI | reg | 0xFE20_0000 | 0xFE2F_FFFF | 1 MB | Std | USB 2.0 XHCI registers |
XRAM_CTRL0 | reg | 0xFF8E_0000 | 0xFF8E_FFFF | 64 KB | XRAM | XRAM Bank 0 control |
XRAM_CTRL1 | reg | 0xFF8F_0000 | 0xFF8F_FFFF | 64 KB | XRAM | XRAM Bank 1 control |
XRAM_CTRL2 | reg | 0xFF90_0000 | 0xFF90_FFFF | 64 KB | XRAM | XRAM Bank 2 control |
XRAM_CTRL3 | reg | 0xFF91_0000 | 0xFF91_FFFF | 64 KB | XRAM | XRAM Bank 3 control |
XRAM_INT_GPV | reg | 0xFF94_0000 | 0xFF94_FFFF | 64 KB | XRAM | XRAM Interconnect Global Programmers View (GPV) |
XRAM_SLCR | reg | 0xFF95_0000 | 0xFF95_FFFF | 64 KB | XRAM | XRAM System-level control |
XRAM_XMPU0 | reg | 0xFF93_0000 | 0xFF93_3FFF | 16 KB | XRAM | XRAM Memory Protection Unit 0 |
XRAM_XMPU1 | reg | 0xFF93_4000 | 0xFF93_7FFF | 16 KB | XRAM | XRAM Memory Protection Unit 1 |
XRAM_XMPU2 | reg | 0xFF93_8000 | 0xFF93_BFFF | 16 KB | XRAM | XRAM Memory Protection Unit 2 |
XRAM_XMPU3 | reg | 0xFF93_C000 | 0xFF93_FFFF | 16 KB | XRAM | XRAM Memory Protection Unit 3 |
XRAM_mem | mem | 0xFE80_0000 | 0xFEBF_FFFF | 4 MB | XRAM | On-chip Accelerator RAM, 4 MB |