APB, AXI Programming Interfaces

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The PMC, PS/PSX, and CPMx interconnect enables software to access the APB and AXI-based control and status registers. Most functional units use an APB programming interface; some use an AXI interface. The programming interfaces are scattered throughout the platform management system and processing system interconnect. The access to the programming interfaces is protected with fixed security and programmable security provided by XPPU and XMPU protection units.

The register modules are accessed using 32-bit read/write transactions on the AXI interconnect. The transactions are usually routed through an XPPU or XMPU protection unit and then to a local APB switch for distribution to the APB programming interfaces. The AXI programming interfaces connect to AXI switches. Several register modules are always secure and can further restrict access to them.

Interrupts from each functional unit are signaled directly to the system interrupt controllers in the FPD, LPD, PMC, and to the PL fabric.

Memory-mapped Register Access Types

The memory-mapped (MM) register can be read, write, or have another access type as shown in the following table.

Table 1. Memory-mapped Register Access Types
Access Type Description
R Read-only
W Write-only
RW Read and write
WTC or W1C Write 1 to clear (readable unless noted)