APU MPCore Functional Units

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

Processor Pipelines

There are several pipelines and engines in the APU:

L1 Caches

Each processor includes its own local L1 cache connected to the SCU and L2-cache memory.

Cache features include:

  • 48 KB instruction cache protected with parity and includes a 48-entry fully associative TLB
  • 32 KB data cache protected with ECC and includes a 32-entry fully associative TLB

L2 Cache

The 1 MB, unified L2 cache with ECC is physically addressed and physically tagged.

  • 4-way set associative 1024-entry TLB
  • PL can be coherent using S_ACE_FPD, S_ACP_FPD, S_AXI_HPC, NSU2, and NSU3 interfaces
  • CPM can be coherent using ACE-Lite port via SMMU TBU 3