APU Processor Implementations

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2023-10-05
Revision
1.6 English

The implementation of the APU processor engine components are listed in the following tables.

Table 1. APU Processor Implementations, Part 1
Device Generation Application Processor Unit (APU) CPU Core Extensions CPU System Extensions APU Caches
AMD UltraScale+™ MPSoC Four-core Cortex-A53 processor, v8-architecture SIMD, VFPv4 floating-point Cryptography 32 KB iCache, 32 KB dCache, 1 MB L2-cache within CCI
AMD Versal™ adaptive SoC Two-core or four-core Arm® Cortex-A72, v8-architecture

Version r0p3-00rel0

NEON and VFPv4 floating point A74-MP and MP054

Version 0p1-50eac0

A72-Crypto extension MP055

Arm version r0p2-00rel0

48 KB iCache, 32 KB dCache, 1 MB L2-cache with CCI
Table 2. APU Processor Implementations, Part 2
Device Generation Generic Interrupt Controller (GIC) Embedded Logic Analyzer (ELA) Arm Server Base System Architecture (SBSA) CPU System Interface ACP Interface
UltraScale+ MPSoC GIC-400 tbd No Single 128b ACE port to CCI Yes
Versal adaptive SoC Generic interrupt controller, GIC-500 Arm, v3 architecture

version r1p1-00rel0

Yes Yes Single 128b ACE4 port to CCI Yes