AXI System Interfaces

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID
Release Date
1.6 English

There are several AXI interfaces:

  • Two 64-bit AXI transaction hosts: connect to the OCM switch to access destinations
  • 32-bit AXI destinations: provides access to the RPU GIC interrupt controller
  • 64-bit AXI destinations: provides access to the CPU memories (ICache, DCache, and TCMs)

Access to the caches by other system processors is only available during debug when the CPUs are put into their idle state. The AXI interfaces enable the CPU memory system to have access to peripherals and system memories including OCM and DDR.