AXI System Interfaces

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

There are several AXI interfaces:

  • Two 64-bit AXI masters: connect to the OCM switch to access system slaves
  • 32-bit AXI slave: provides access to the RPU GIC interrupt controller
  • 64-bit AXI slave: provides access to the CPU memories (ICache, DCache, and TCMs)

Access to the caches by other system masters is only available during debug when the CPUs are put into their idle state. The AXI master interfaces enable the CPU memory system to have access to peripherals and system memories including OCM and DDR.