AXI Transaction Control

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The AXI transactions generated by the DMA master can be configured for bufferability and coherency.

Table 1. GEM AXI Transaction Control Registers
LPD Register Name Offset Address Access Type Description
Coherency


            GEM0_Coherent
        


            GEM1_Coherent
        

0x0324
0x0344

RW

Select cache coherency policy.

Routing


            GEM0_Route
        


            GEM1_Route
        

0x0328
0x0348

RW

Enable transaction to be routed to CCI.

QoS


            GEM0_QoS
        


            GEM1_QoS
        

0x032C
0x034C

RW

Select QoS bit values