Address Maps

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The address maps are divided into three types:

  • High-level address map
  • PMC and processing system address map
  • NoC address map

High-Level Address Map

The high-level address map includes groups of register modules and memory spaces within the entire memory range.

  • Versal device 16 TB, 44-bit physical address

4 GB Address Maps

The 4 GB address map can be divided into two sections:

  • First 2 GBs for DDR memory
  • Second 2 GBs of destinations in the platform management controller (PMC), processing system, and the majority of the CPM register modules, if present

The 4 GB address map includes register modules, local memories, miscellaneous access ports, and small windows in the interfaces directly from the processing system to the programmable logic (PL). This address space also includes destinations in the cache coherent PCIe module (CPM), when present.

There are two 2 GB address tables with the same content. One is organized by address and the other is organized by destination name.

NoC Address Map

The NoC address map includes all of the destinations within the device for access to DDR, and optional hardware including AI Engine, video decoder unit, and many different peripherals.

Types Destinations

The local address maps include a type column that characterizes what is contained within the memory range. The types include:

  • mem: read/write memory location
  • reg: register modules listed in the register manual; these use an APB or AXI programming interface
  • local: the address space is only accessible to a local processor
  • mmap: miscellaneous memory mapped destinations that include memory and register modules
  • port: data write or streaming data interface

Device Options

Not all devices have the destinations listed in the address maps. The options vary by device series and devices within a series.

See the Integrated Hardware Options section for general descriptions. For a comprehensive list of what options are available in each device, see the Versal ACAP product data sheets listed in References.

The address maps include a column to indicate if the destination is part of an optional feature:

  • Std means available in every device in the series
  • XRAM accelerator RAM device option
  • DDRMC DDR memory controller (all devices have at least one DDR memory controller; Std)
  • CPM4 device option
  • CPM5 device option

The options for each device are itemized in the Versal Architecture and Product Data Sheet: Overview (DS950).

Security Access

The information for certain individual registers and full register sets are only available from the Design Security Lounge in the Versal ACAP Security Register Reference Manual (AM018) register manual and the Versal ACAP Security Manual (UG1508). Access to the Design Security Lounge requires an active NDA.

In the following two address map tables, there are five register sets with restricted access. These are identified as controlled under NDA. The PMC_CACHE registers are mostly controlled under NDA. The PMC_EFUSE_CTRL register set is partially controlled under NDA.