Agent Interrupt Registers

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID

AM011

Release Date

2023-10-05

Revision

1.6 English

The IPI interrupt registers are listed in the following table. The base address is 0x0FF30_0000. These registers have access restriction based on the processor's SMID and settings in the IPI.TZ_APER_INTR register.

The IPI processor interrupt management registers are not affected by the IPI register LOCK control register.

Table 1. IPI Processor Interrupt Management Registers
Register Name	Offset Address	Access Type	Description
PSM_TRIG PSM_OBS PSM_ISR PSM_IMR PSM_IER PSM_IDR	`0x10000`+	W R W1C R W W	PSM agent interrupt registers
PMC_TRIG PMC_OBS PMC_ISR PMC_IMR PMC_IER PMC_IDR	`0x20000`+	W R W1C R W W	PMC agent interrupt registers
IPI0_TRIG IPI0_OBS IPI0_ISR IPI0_IMR IPI0_IER IPI0_IDR	IPI0: `0x30000`+ IPI1: `0x40000`+ IPI2: `0x50000`+ IPI3: `0x60000`+ IPI4: `0x70000`+ IPI5: `0x80000`+ IPI6: `0xA0000`+	W R W1C R W W	Programmable agents for IPI interrupts and messaging Except, IPI 6 does not include message or response buffers
PMC_NOBUF_TRIG PMC_NOBUF_OBS PMC_NOBUF_ISR PMC_NOBUF_IMR PMC_NOBUF_IER PMC_NOBUF_IDR	`0x90000`+	W R W1C R W W	PMC agent interrupt registers without message and response buffers