Application Processing Unit

Versal ACAP Technical Reference Manual (AM011)

Document ID
Release Date
1.5 English

This chapter contains these main sections:

The application processing unit (APU) provides general-purpose computing in a standard programming environment based on powerful and feature-rich Arm® Cortex® -A72 cores with their A64 instruction set in the v8-A architecture. The APU includes two A72 cores. The generic interrupt controller (Arm GIC-500) is added to manage system interrupts. Other processors and DMA units can interact with the APU L2 cache memory with error-correction code (ECC) to form a tightly coupled heterogeneous system using the Cache Coherent Interconnect (CCI). The APU is located in the FPD of the PS.

Note: The APU processors can be used for computations, control-plane applications, operating systems, communications interfaces, and more. The TRM describes the architecture and the programming model for the APU functional units. Linux and bare-metal software stacks execute in the APU and RPU in a homogeneous or a heterogeneous environment. Refer to UG1304 for software topics.

A72 Processor Implementation

The TRM provides an overview of the processor features and implementation notes for the Versal® device. An extensive set of documentation is available from Arm. The introduction to Arm processors and documentation begins at the Arm developer architectures website. The IP version is listed in System Features.