This chapter contains these main sections:
- Features
- System Perspective
- Memory Space
- Execution Pipelines
- APU Address Model
- Virtualization
- Server Architecture
- Processor Counters
- PS FPD Interrupts
- GIC-500 Interrupt Controller
- Register Reference
The application processing unit (APU) provides general-purpose computing in a standard programming environment based on powerful and feature-rich Arm® Cortex® -A72 cores with their A64 instruction set in the v8-A architecture. The APU includes two A72 cores. The generic interrupt controller (Arm GIC-500) is added to manage system interrupts. Other processors and DMA units can interact with the APU L2 cache memory with error-correction code (ECC) to form a tightly coupled heterogeneous system using the Cache Coherent Interconnect (CCI). The APU is located in the FPD of the PS.
A72 Processor Implementation
The TRM provides an overview of the processor features and implementation notes for the Versal® device. An extensive set of documentation is available from Arm. The introduction to Arm processors and documentation begins at the Arm developer architectures website. The IP version is listed in System Features.