The cacheability of a transaction is used by the CCI to determine if a cache look-up is required and if there is a hit, what to do with the read or write data.
The cache and buffer policy for a transaction is encoded in four AxCACHE signals. There are two separate sets of signals for reads and writes. The four AxCACHE signals are driven from register bits and are defined as follows when the bit is set High.
- Bufferable, bit : interconnect can delay transaction before reaching its destination; most relevant to writes
- Cacheable, bit : transaction is not compared to the APU L2-cache by the CCI
- Read Allocate, bit : a cache miss allocates space for the read data from system memory
- Write Allocate, bit : a cache miss allocates space for the write data from the initiator
The four AxCACHE [3:0] bits are combined together.
0000: non-cacheble and non-bufferable
0001: bufferable only
0010: cacheable but does not allocate
0011: cacheable and bufferable, does not allocate
0110: cacheable write-through, allocates on read
0111: cacheable write-back, allocates on read
1010: cacheable write-through, allocates on write
1011: cacheable write-back, allocates on write
1110: cacheable write-through, allocates on both read and write
1111: cacheable write-back, allocates on both read and write
Many PS peripheral transaction hosts can be programmed to route their transactions directly to DDR memory or to the APU SMMU and the CCI first. The AxCACHE attributes are valid when the transaction is routed through the SMMU and CCI.
- RPU processors
- LPD DMA controllers
- SD_eMMC, OSPI, GEM controllers