Basic Window Programming Sequence

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The programming steps for the basic window mode are provided in this section.

  1. If required, set the [WDP] bit to enable protection against accidental clearing of the [WEN] bit. The [WDP] bit does not affect being able to set the [WEN] bit to = 1.
  2. Configure the two window count registers First_Wind and First_Wind according to the requirements of the application.
  3. Set the interrupt position in the second window according to the requirements using the Funct_Ctrl [SBC] and [BSS] bit fields. Refer to the top of the Windowed Waveform Diagram) or the explanation in the register manual.
  4. If required, enable the Fail Counter.
  5. If required, enable the Basic Program Sequence Monitor, PSM.
  6. If required, enable the Second Sequence Timer, SST.
  7. If the PSM is enabled, write to the Task_Sig0 register, TSR.
  8. Enable the watchdog timer by setting the Enable_and_Status [WEN] bit = 1. This auto-clears the WProt [MWC] bit to make the address space read-only and generates the first restart of the watchdog timer.

    After completing the first window, the watchdog enters in the second window period and the timer sets the Enable_and_Status [WSW] bit. Software might generate the next restart (or it might disable the watchdog timer) any time after the [WSW] bit is set.

    The Task_Sig1 , TSR1, register can be written any time irrespective of whether the [WSW] bit is set or not (enable [MWC], write Task_Sig1 , and disable [MWC]). The TSR0 and TSR1 register comparison is done at the restart or disable event if the PSM is enabled.

  9. Wait for the watchdog system interrupt.
  10. Enable the [MWC] and restart or disable the watchdog according to the requirement:
    • clear [WINT], [WSW], or
    • clear [WINT], [WSW], [WDP], [WEN]
    • If software attempts to restart or disable the watchdog in the first window, it is considered a bad event. The disable request is not honored.
    • If software does not restart or disable the watchdog before the second window ends, it is considered a bad event.
    • If a PSM is enabled and a TSR mismatch was detected at the restart or disable time in the second window, it is considered a bad event. If the PSM is disabled, the TSR values are not compared.
    • If the fail counter is disabled, a single bad event leads to the subsystem reset. The [LBE] bit field stores the last bad event. The [LBE] bit field can be cleared by asserting a reset to the watchdog timer.
    • If software restarts/disables the watchdog in the second window, it is considered a good event.
    • If the fail counter is enabled, a good event decrements the fail counter by 1 unless it is 0, and a bad event increments the fail counter by 1 unless it is 7.
    • If the fail counter is 7 and a bad event occurs, this leads to the subsystem reset. The assertion is delayed if the Second Sequence Timer is enabled with the [SSTE] bit.
    • The Fail Counter status can be read by reading the Enable_and_Status [FCV] bit field.
  11. If the watchdog is restarted, it starts with a new cycle with the first window.
Note: After generating the system reset, the watchdog timer stops running and the [WEN] bit auto-clears.