Block RAM

Versal ACAP Technical Reference Manual (AM011)

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1.4 English

Several of the block RAM key features are listed in this section. For additional features and functionality, see the Versal ACAP Memory Resources Architecture Manual (AM007).


Synchronous Operation
Each memory access, read, and write is controlled by the clock. All inputs, data, address, clock enable, and write enable are registered. The data output is always latched, retaining data until the next operation. An optional output data pipeline register allows higher clock rates at the cost of an extra cycle of latency. During a write operation, the data output can be made to reflect the previously stored data, the newly written data, or remain unchanged. There is independent reset control of output latches and registers.
Asynchronous Operation
The data outputs can also be set or reset asynchronously. Sleep input (places array in low power state) can be optionally asynchronous.
True Dual-port Operation
The block RAM has two completely independent ports that share nothing but the stored data.
Simple Dual-port Operation
One port is dedicated as a write port and the other as a read port. Consequently, the data width can be extended to 72 bits for the 36 Kb full block RAM or 36 bits for the "split" 18 Kb block RAM.

Cascade mode supports all configurations available in 36 Kb RAM or 18 Kb RAM. Cascading refers to combining multiple block RAMs to build larger ones, without using additional logic resources.

Each 64-bit-wide block RAM can generate, store, and use eight additional bits to perform single-bit error correction and double-bit error detection (ECC) during the read process. The ECC logic can also be used when writing to, or reading from, external 64- or 72-bit-wide memories. Block RAM contents can be initialized or cleared by the configuration bitstream.

Comparison to Previous Generation Xilinx Devices

The block RAM has several notable differences compared to the block RAM in the UltraScale+™ device. Several features are removed, including x1, x2, x4 widths, hard FIFO (can be instantiated), address enable/compare, and systolic cascade. See the Versal ACAP Memory Resources Architecture Manual (AM007) for a complete list, including a few changes and enhancements.