Boot Header Register Initialization Feature

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The Boot Header includes the register init segment that can hold the address and data for writing up to 256 registers during the BootROM process. The boot header can include register writes to configure and optimize the system based on the boot mode.

The register address space for register initialization address-data writes is restricted by the BootROM for both non-secure and secure boot modes. Register addresses outside of the allowed address range cause the BootROM to lock down the system and generate BootROM error code 0x400. The allowed register accesses depend on the boot mode and are listed in the following table. These restrictions are enforced by the BootROM. They do not apply when the PLM/user code begins to execute. The BootROM screens the register initialization writes and does not allow certain addresses to be accessed.

Note: For the accessible ranges, there are reserved register locations within a register module that should not be written.
Table 1. BootROM Address Ranges for Register Initialization
  Address Ranges Accessible
PMC_GPIO
  0xF102_0000 to 0xF102_0324 Yes
PMC_I2C
  0xF100_0000 to 0xF100_0030 Yes
QSPI
 

0xF103_0000 to 0xF103_01FC

No: miscellaneous controller registers
0xF103_0200 to 0xF103_0828 Yes: DMA address and control registers
OSPI
 

0xF101_0000

Yes: controller configuration

0xF101_0004 to 0xF101_00FC

No: miscellaneous controller registers
0xF101_0100 to 0xF101_1FF8 Yes: DMA address and control registers, safety check
SD_eMMC0 1
  0xF104_0000 Yes: Low DMA address register

0xF104_0004 to 0xF104_0054

No: miscellaneous registers

0xF104_0058 to 0xF104_005C

Yes: Low DMA address register

0xF104_0060 to 0xF104_00FC

No: miscellaneous registers

0xF104_0100 to 0xF104_F0FC

Yes: TAP delay registers
SD_eMMC1 1
  0xF105_0000 Yes: Low DMA address register

0xF105_0004 to 0xF105_0054

No: miscellaneous registers

0xF105_0058 to 0xF105_005C

Yes: Low DMA address register

0xF105_0060 to 0xF105_00FC

No: miscellaneous registers

0xF105_0100 to 0xF105_F0FC

Yes: TAP delay registers
CRP
 

0xF126_0000 to 0xF126_0104

No: interrupts, PLLs, routing

0xF126_0108 to 0xF126_014C

Yes: peripheral clocks

0xF126_0150

No: safety check

0xF126_0154 to 0xF126_01FC

Yes, clocks

0xF126_0200 to 0xF126_05CC

No: boot mode, ClkMon, reset, and PL ref clock control
SBI
  0xF126_0000 to 0xF122_030C Yes
PMC_INT_CSR
  0xF133_0068 only Yes
PMC_RAM_CSR
  0xF110_0000 to 0xF110_0FF8 Yes
PMC_IOP_SLCR
  0xF106_0000 to 0xF106_0828 Yes
PMC_SYSMON_CSR
  0xF127_0000 to 0xF127_1F94 Yes
  1. The SD_eMMC registers are described with 8, 16, and 32 bits. However, all registers are implemented and addressed as a 32-bit word.