Boot Modes

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The Versal® ACAP boot modes are designed for maximum flexibility. This chapter provides a primary boot mode summary, selection considerations, and interface details. The primary boot modes in the PMC are:

Each boot mode uses a set of I/O pins and has a voltage requirement that can affect post-boot peripheral use of shared MIO on a bank. The best overall boot mode solution for an application considers the overall system requirements, performance, cost, and complexity.

The boot modes are categorized into master or slave boot modes. The master boot modes automatically load the programmable device image from a memory source (SD, eMMC, quad SPI, or octal SPI). The master boot modes provide a basic solution with easy setup. In master boot modes, the POR_B pin release to the first fetch from a boot device is estimated at ~620 μs. This time guides how quickly the flash must be ready to respond to the BootROM. The slave boot modes require an external processor or controller to load the programmable device image with a command set (JTAG or SelectMAP). An advantage of using a slave boot mode is that the device image can reside almost anywhere in the host system or over a network connection. The slave boot modes are multipurpose interfaces that can also be used for system debug and readback.

For systems that require a low-cost solution, QSPI boot modes are ideal with a variety of second-source vendors. For applications that require faster boot times due to power-on latency constraints, the boot modes with wide bus widths are inherently faster. For the master boot modes, the QSPI dual-parallel 8-bit or OSPI 8-bit is an optimal choice for a faster boot time. For slave-boot modes, the SelectMAP 32-bit mode provides the fastest option. For applications with large storage capacity requirements, the SD and eMMC1 boot modes support larger boot memory devices.

The Versal ACAP MIO-at-a-glance table should be reviewed to ensure that the requirements for boot and post-boot peripherals are satisfied. This chapter focuses on the primary boot mode options, however, the Versal ACAP is capable of starting with a primary boot mode and then switching to a secondary boot option (i.e., QSPI primary boot, followed by eMMC0 as a secondary boot option to provide larger density and flexibility). See the Versal ACAP System Software Developers Guide (UG1304) for more information on secondary boot options. The following table lists the available primary boot modes. Boot modes that are secure boot capable support both Asymmetric and Symmetric Hardware Root of Trust modes.

Table 1. Primary Boot Modes
Mode MODE[3:0] Pins PMC I/O Pins Secure Boot Capable Data Bus Width Description
Interfaces controlled by external devices
JTAG 0000 Dedicated I/O No 1-bit Dedicated JTAG interface
SelectMAP 1010 MIO[51:28, 25:14] Yes 8-bit, 16-bit, 32-bit SelectMAP bidirectional parallel data bus interface
Interfaces controlled by on-chip controllers
OSPI 1000 MIO[12:0] Yes 8-bit Octal SPI interface supports single and dual-stacked flash devices
QSPI24 0001 MIO[12:0] Yes 1-bit, 2-bit, 4-bit

(single or dual-stacked)

8-bit (dual-parallel)
Quad SPI interface supports the 24-bit (3-byte) flash addresses 1
QSPI32 0010 MIO[12:0] Yes 1-bit, 2-bit, 4-bit

(single or dual-stacked)

8-bit (dual-parallel)
Quad SPI interface supports the 32-bit (4-byte) flash addresses. 32-bit flash addressing is required to address flash devices that are greater than 128 Mb. 1
eMMC1 (4.51) 0110 MIO[12:3,0] Yes 1-bit, 4-bit, 8-bit eMMC interface supports eMMC 4.51 at 1.8V
SD0 (3.0) 0011 MIO[49:37] Yes 4-bit SD interface supports SD 3.0 with a required SD 3.0 compliant external level shifter
SD1 (2.0) 0101 MIO[51:50,33:28, 26] Yes 4-bit SD interface supports SD 2.0
SD1 (3.0) 1110 MIO[51:50, 36:26] Yes 4-bit

SD interface supports SD 3.0 with a required SD 3.0 compliant external level shifter

  1. For Quad SPI single flash or dual-stacked flash setups, only a subset of the MIO interface pins listed are required and the MIO interface pins can be used for other peripherals. See the boot interface diagrams for more information.

Boot Pin Usage Guide

The following table illustrates the MIO pins needed for each boot mode. All MIO interfaces are summarized in the tables in the MIO-at-a-Glance section.

Table 2. Boot Pin Usage Summary Table
MIO Pin 0 1:2 3:11 12 13 14:25 26 27 28:33 34 35 36 37:49 50:51
Pin Count 1 2 9 1 1 12 1 1 6 1 1 1 13 2
Octal SPI 0:12 - -
Quad SPI 0:12 - -
SD0 (3.0) - - 37:49 -
SD1 (2.0) - 26 - 28:33 - 50:51
SD1 (3.0) - 26:36 - 50:51
eMMC1 0 - 3:12 - -
SMAP 8 bit - 14:25 -
16-bit - 14:25 - 28:35 -
32-bit - 14:25 - 28:51

Boot Mode Search Limits

The BootROM has a search limit to locate the device image boot header for every boot mode. If a boot mode search limit is reached without a successful boot, the RCU goes into lockdown and the ERROR_OUT pin is set. The following table lists the boot image search limits for each mode.

Table 3. Boot Mode Search Limit
Boot Mode Search Offset Limit
OSPI (single, dual-stacked) 8 Gb
QSPI24 (dual-parallel) 256 Mb
QSPI24 (single, dual-stacked) 128 Mb
QSPI32 (dual-parallel) 8 Gb
QSPI32 (single, dual-stacked) 4 Gb
SD0 (3.0), SD1 (2.0), SD1 (3.0), or eMMC1 8191 FAT files (default)
eMMC1 (raw) eMMC device size
Note: When using OSPI or QSPI dual-stacked mode, the BootROM can only access the lower QSPI or OSPI addressable flash memory space for boot. After boot, the PLM can access the upper QSPI or OSPI for additional image storage.