CCI CSR

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The CCI core registers are summarized in the following table.

Table 1. CCI CSR Register Set Overview
Register Name Access Type Description
APB_ERR_CTRL RW APB transaction error signal enable


            APB_MISC_ISR
        

            APB_MISC_IMR
        

            APB_MISC_IER
        


            APB_MISC_IDR
        

WTC
R
W
W

APB address decode error and event counter overflow interrupts
CCI_MISC_CTRL RW CoreSightâ„¢ debug enables invasive/secure