CCI Core

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The CCI core registers are summarized in the following table.

Table 1. CCI Core Register Set Overview
Register Name Access Type Description
ctrl_ovr RW Fail-safe overrides
secr_acc RW Non-secure transaction access enables
status R Snoop enables timings
impr_err RW Imprecise signaled errors
qos_threshold RW Read and write QoS thresholds for high-priority requests
pmu_ctrl RW, R Performance monitoring unit controls
Egress Port Control for Six Ports


            snoop_ctrl_si0
        

(0 to 5 egress ports)

RW, R Snoop and DVM request issue control


            share_ovr_si0
        

(0 to 5 egress ports)

RW Override shareable characteristics of normal transaction


            arqos_ovr_si0
        

(0 to 5 egress ports)

RW Override value for reads


            awqos_ovr_si0
        

(0 to 5 egress ports)

RW Override value for writes


            qos_max_ot_si0
        

(0 to 5 egress ports)

RW Permitted outstanding transactions (OT)
Event Control for Eight Event Modules


            evnt_sel_0
        

(0 to 7 event modules)

RW Event codes for events and interface


            ecnt_data_0
        

(0 to 7 event modules)

RW Event counter value


            ecnt_ctrl_0
        

(0 to 7 event modules)

RW Event counter enable


            ecnt_clr_ovfl_0
        

(0 to 7 event modules)

RW Event overflow flag