CPM4 Module

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2023-10-05
Revision
1.6 English

The Cache Coherent Interconnect for Accelerators (CCIX) block is coupled with two PCIe┬« blocks, a DMA unit, and an L2 cache to create the CPM4. The CPM4 includes a 1 MB CPM L2-cache.