The settings for the threshold NCLKMON_THRESH registers depends on the following parameters:
- Frequency of the base clock, FBASE_CLK
- Number of base clocks programmed for the base time period, NBASE_CLK_CYCLES
- Frequency threshold of the monitored clock, FMON_CLK
A threshold setting can be calculated using the following equation:
In this example, the following is assumed:
- REF_CLK is used with a 33 MHz clock frequency
- CLKMON0_BASE [CLK_CYCLES] is set = 10000
- Desired lower threshold frequency for the APU clock is 1000 MHz
Because the APU clock is divided by 4 before being presented to the ClkMon channel (see table in Monitored Clocks), the FMON_CLK is actually 250 MHz.
From the equation, the clock threshold is
1_27EDh (75,757d). Bound the accuracy using ClkMon 0 by programming
and CRP.CLKMON0_THRESH_H registers.
The sampling time is approximately 303 ms.