Each [CRnn] bit of the TX Buffer Cancel Request ( Tx_Buff_Cancel_Req ) register corresponds to a message element in the TX buffer (and, consequently, corresponds to a TxBuff_Ready_Req [RRnn] bit).
- Poll the TxBuff_Ready_Req register (TRR) to check current pending transmission requests.
- Poll the
to check current pending cancellation requests.
- Transmit cancellation for a buffer (TXB_i) can be requested only if there is a corresponding pending transmission request set in the TRR register.
- If there is already a pending cancellation request for TXB_i, no action is required and the host should wait (by poll/interrupt) until the core serves a cancellation request for TXB_i.
- If the TXB_i buffer has a pending transmission request but no
pending cancellation request, then transmit cancellation can be requested as
- Enable interrupt generation as required.
- Set the required TCR [CRnn] bit(s). The software can request the cancellation of multiple buffers with one write to the TCR register.
- Wait for the interrupt or poll the TCR register to determine the cancellation status.
- The controller clears the bit in the TCR register when the respective buffer transmit cancellation request is completed.
- The controller also clears the corresponding bit in the TRR register when cancellation is performed.
- The controller performs the cancellation of a buffer immediately
- When the buffer is locked by the transfer layer for transmission on the CAN bus. In this case, cancellation is performed at the end of the transmission irrespective of whether the transmission is successful or not (arbitration loss or error).
- When the core is performing a scheduling round to find out the next buffer for transmission. In this case, cancellation is performed after the scheduling round is finished.
- The controller clears the respective bits in the Tx_Buff_Cancel_Req and TxBuff_Ready_Req registers when cancellation is done.
- If enabled through the TxBuff_Ready_Req_Intr_En (IETRS) or APB_MISC_IER (IER) registers, then the APB_MISC_ISR [TXRRS] bit is set = 1 (when the controller clears the bit in the Tx_Buff_Cancel_Req register) and an interrupt is generated.