A DMA channel reading from a flow controlling the PL destination scenario is similar to the suggested use model except the one-to-one correlation between SRC and DST AXI commands does not exist. The number of commands generated on the SRC side can be different than the DST. In this case, the number of transaction valid responses can be less/more than the number of credits used. Unless the software calculates the number of valid transactions required for DMA transfer, the PL memory cannot use the valid transactions.
The DMA channel only generates read data transactions if credit is available. After it has enough data to generate a write transaction, it issues a write command. The destination can snoop on the AXI read channel to keep track of the number of beats/bytes read by the DMA channel.