Clock Monitor

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The clock monitor (ClkMon) includes eight independent channels to detect when a clock is out of its expected frequency range. The ClkMon does this by counting the number of clock cycles from the monitored clock that occur during a known base time period. A channel asserts an interrupt if the number of clock cycles detected during a base time period is more than the upper threshold count, or less than the lower threshold count. The ClkMon is located in the PMC.

The length of the base time period is programmed by selecting a reference clock and defining the number of clock periods to use. The base clock source is selectable, REF_CLK or PMC_IRO_CLK. The base time period is typically 100 to 10,000 clock cycles long, depending on the application and which clocks source is used. A longer base time period results in higher accuracy, but the monitoring time period is longer.

A channel monitors one of 16 clocks located in the PMC, LPD, or FPD, as listed in Monitored Clocks. During the base time period, the ClkMon channel counts the clock cycles of the monitored clock. The channel can be started to capture the clocks in one time period or sample the clock over and over again. At the end of a time period, the monitored clock cycle count is compared with the upper and lower threshold registers. If the number of clock cycles is out of range, an interrupt is generated.