Clock and Reset Control

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The persistent clock and reset registers are summarized in the following table.

Table 1. Persistent Clock and Reset Control Registers
Register Offset Address Description
PMC CRP Clock and Reset Register Module


            BOOT_MODE_USER
        


            RESET_REASON
        

0x0200
0x0220

Software boot mode control and status.
Source of the last reset (POR_B required).


            RST_PS
        


            RST_NONPS
        


            RST_DBG
        

0x031C
0x0320
0x0400

Resets: [PMC_POR], [PS_POR], [PL_POR] only. Non-PS, PMC resets: [SOC_POR] only. Reset for Debug blocks.
LPD CRL Clock and Reset Register Module


            RST_CPU_R5
        


            RST_DBG_LPD
        


            RST_FPD
        

0x0300
0x0338
0x0360

RPU
               Cortex®-R5F
hard reset: [RESET_PGE].
Debug, HSDP,
               CoreSight™
            
resets.
FPD reset.

FPD CRF Clock and Reset Register Module


            RST_APU
        


            RST_DBG_FPD
        


            RST_FPD_SWDT
        

0x0300
0x030C
0x0314

APU
               Cortex®-A72
hard resets: [APUx_PWRON].
SoC debug reset.
FPD system watchdog timer reset.