Clock and Reset Registers

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The USB reference clock and core reset are controlled by the CRL register module. The base address for the CRL register module is 0xFF5E_0000.

Table 1. Clock and Reset Registers for USB
Register Name Offset Address Access Type Description
Reference Clock


            USB_LPD_REF_CTRL
        

0x0124

RW Reference clock control from LPD clock controller
Controller Reset


            RST_USB_2
        

0x0314

RW Controller reset from LPD reset controller