Clocks

Reference Clock

Most devices require a single REF_CLK. Several stacked silicon integrated (SSI) technology devices require two reference clocks, REF0_CLK and REF1_CLK. For additional information, see the Versal ACAP PCB Design User Guide (UG863).

PMC and PS Clocks

The clocks associated with the PMC and PS are described in the following sections:

• The Clock Distribution Diagram shows the major internal clocks for the PMC and PS (LPD and FPD)
• Three PMC Source Clocks originate in the PMC:
  • REF_CLK (reference clock input device pin)
  • PMC_IRO_CLK (PMC internal ring oscillator)
  • RTC (real-time clock)
• Five programmable PLL Clock Generators: two in the PMC and one in the LPD, FPD, and CPM
• Dozens of programmable Reference Clock Frequency Dividers are used to generate clocks for various blocks in the system

CPM Clocks

The clocks for the CPM are described in the Versal ACAP CPM CCIX Architecture Manual (AM016).

NoC, AI Engine, and DDR Memory Controller Clocks

The PMC includes four programmable clock dividers with outputs routed to the PL for general purpose usage. The PMC also includes programmable clock divider outputs for the NoC, AI Engine, and DDR memory controllers.

PL Clocks

The PL includes its own clock arrays that are programmed when blocks are instantiated. The PL also includes programmable clock modules that can be driven by clocks from input pins and other sources.

I/O Transceiver Clocks

There are local PLLs in the XPIO banks (for the PL, XPHY, and DDRMC) and the gigabit transceivers (GT). These high-speed I/Os use PLL clocks for precision I/O timing. These I/O buffers and transceivers are introduced in the Device I/O Connectivity chapter of the Hardware Architecture section. The I/O transceiver clocks are described in their associated documents:

• GTY and GTYP transceiver PLLs: Versal ACAP GTY and GTYP Transceivers Architecture Manual (AM002)
• XPIO bank XPLLs: Versal ACAP SelectIO Resources Architecture Manual (AM010)

Clock Register Modules

The individual clock controls are managed by the PLM firmware. The PLM writes to the clock and reset register modules.

• CRP : device-level and individual PMC block clock control registers
• CRL : subsystem and individual LPD block clock control registers
• CRF : subsystem and individual FPD block clock control registers
• CPMx_CRX: individual CPM block clock control registers