Comparison to MPSoC Generation Devices

Versal ACAP Technical Reference Manual (AM011)

Document ID
Release Date
1.5 English

The SD/eMMC controller is similar in the Zynq® UltraScale+™ MPSoC devices.

Improvements and changes:

  • Enhanced DLL with new programming model
  • DLL is used for all frequencies above 25 MHz
  • Separate SD 0 and 1 register sets for the DLL TAP delays
  • Maximum frequency with external level shifter bumped from 19 to 20 MHz
  • Tuning count default value changed from 32 to 40
  • SD_REF_CLK divider set = 0 results in a divide by 1