The FPD includes the Arm CCI-500 cache coherency interface IP. There are some notable differences to the CCI-400 in the AMD Zynq™ UltraScale+™ MPSoC.
The CCI-500 provides a snoop filter that keeps a record of the addresses stored in the attached caches. The snoop filter can often resolve coherency messaging without broadcasting the inquiry to all ACE interfaces.
The CCI-500 does not support QVN. To support low-latency (LL) and best effort (BE) quality of service (QoS) traffic simultaneously through the CCI effectively, the CCI uses a custom address decode scheme that is optionally enabled via register programming.