Configuration Frame Unit

Versal ACAP Technical Reference Manual (AM011)

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1.4 English

The configuration frame unit (CFU) translates AXI traffic into the CFI bus protocol, performs data integrity checks, and manages the CFI traffic. The CFU also performs several functions including frame write rate matching, frame read rate matching, frame read/write transition, row switching, decompression, and putting the configuration frame interface (CFI) into idle.

The CFU is the only master for the CFI bus. The input CFU reference clock runs at the same rate as the output CFI clock frequency. The CFU AXI interfaces support 32-bit, 64-bit, or 128-bit transactions. The CFU AXI must 128-bit align the 32-bit and 64-bit transactions. The CFU cannot support multiple AXI masters at the same time. A single master can control both CFU AXI write and read to perform CFI readback.

The programmable device image (PDI) created with the Vitis™ tool contains PL partition data that the CFU manages. The CFU handles the transfer of configuration data through the CFI to the configuration frames in the PL. The CFU ensures that the configuration frames are ready to accept the CFI bus transactions sent to them. The CFU checks the packet data to determine if the packet rate sent needs to be slower and throttles the AXI interface as necessary. The CFU also performs data decompression on the PL_CFI partition included in the .RCDO. PDI compression is set by default in the Versal® device. For more information on changing the compression option, see Vivado Design Suite User Guide: Programming and Debugging (UG908).

The CFU includes a programming interface to the CFRAMExx_REG register modules. These are used to configure the functionality, poll status, and generate PL global signal sequences. The CFU provides several configuration frame data-in ports (CFRAMExx_FDRI) and a configuration frame data-out port (CFU_FDRO).

CFU Address Map

The PL configuration address space includes the following.

  • Register modules
    • CFU_APB (aka CFU_CSR) at 0xF12B_0000
    • CFRAMExx_REG control and status registers (see following table)
  • Data ports
    • CFU_STREAM at 0xF12C_0000, 4 KB
    • CFU_SFR at 0xF12C_1000, 4 KB
    • CFU_FDRO data-out port at 0xF12C_2000, 4 KB
    • CFRAMExx_FDRI data-in ports, 4 KB each (see following table)
Note: The number of configuration frames is based on the size of the PL and is dependent on the device.
Table 1. Configuration Frame Register and Data-In Port Address Map
Configuration Frame Number Register Name Register Address Frame Port Name Frame Port Input Address
0 CFRAME00_REG 0xF12D_0000 CFRAME00_FDRI 0xF12D_1000
1 CFRAME01_REG 0xF12D_2000 CFRAME01_FDRI 0xF12D_3000
2 CFRAME02_REG 0xF12D_4000 CFRAME02_FDRI 0xF12D_5000
3 CFRAME03_REG 0xF12D_6000 CFRAME03_FDRI 0xF12D_7000
4 CFRAME04_REG 0xF12D_8000 CFRAME04_FDRI 0xF12D_9000
5 CFRAME05_REG 0xF12D_A000 CFRAME05_FDRI 0xF12D_B000
6 CFRAME06_REG 0xF12D_C000 CFRAME06_FDRI 0xF12D_D000
7 CFRAME07_REG 0xF12D_E000 CFRAME07_FDRI 0xF12D_F000
8 CFRAME08_REG 0xF12E_0000 CFRAME08_FDRI 0xF12E_1000
9 CFRAME09_REG 0xF12E_2000 CFRAME09_FDRI 0xF12E_3000
10 CFRAME10_REG 0xF12E_4000 CFRAME10_FDRI 0xF12E_5000
11 CFRAME11_REG 0xF12E_6000 CFRAME11_FDRI 0xF12E_7000
12 CFRAME12_REG 0xF12E_8000 CFRAME12_FDRI 0xF12E_9000
13 CFRAME13_REG 0xF12E_A000 CFRAME13_FDRI 0xF12E_B000
14 CFRAME14_REG 0xF12E_C000 CFRAME14_FDRI 0xF12E_D000