Configuration Registers

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The RPU_DUAL_CSR register set includes several control and configuration registers for the RPU. These registers are read/write.

Table 1. RPU Configuration Registers
Register Bit Field and Description Reset Value and Description
GLOBAL_CNTL

[CFGEE, 0]: endian mode during exception handling
[CFGIE, 1]: endian mode for  instruction fetch
[DBGNOCLKSTOP, 2]: CPU clk gate in standby
[SLSPLIT, 3]: Lock-step or Dual processor mode
[SLCLAMP, 4]: Output clamping (RPU0  processor)
[TEINIT, 5]: Exception handling state at reset
[TCM_COMB, 6]: TCM configuration
[TCM_WAIT, 7]: Waitstate for TCM access
[TCM_CLK_CNTL, 8]: Gate clocks to TCMs
[GIC_AXPROT, 10]: AxPROT[1] bit to GIC

0: little endian
0: little endian
0: clock can be gated
0: lock-step mode (safety)
1: clamping enabled
0: Arm instructions
1: TCMs combined (256 KB)
0: no waitstates
0: clocks to TCMs not gated
0: secure transactions


            RPU0_CONFIG
        

and

            RPU1_CONFIG
        

[nCPUHALT, 0]: State after reset released
[VINITHI, 2]: Instruction fetch location after reset
[CFGNMFI, 3]: FIQ masking for RPU0

1: processor runs (not halted)
1: executes from OCM
0: enable FIQ masking