Configuration Restrictions

• In addition to the above registers, the AHB_Indirect_Addr register must be programmed so there is not a 4 KB boundary crossing between the value programmed and the value + 63.
• The Indirect_Read_Num register should be programmed so that the number of bytes read is word-aligned. Bits 1 and 0 should always be programmed to 0 for this register.
• Program the DMA_TOP and then trigger the indirect read transfer using IND_READ_CTRL [start].
• For direct transfers, all the AXI transactions must be aligned.
• For direct write transfers, only the following WSTRB are supported.

Architecture

The AHB interface is used to transfer data, either in a memory mapped direct fashion, or in an indirect fashion where the controller is set up via configuration registers to silently perform some requested operation, signaling its completion via interrupts or status registers.

For indirect operations, data is transferred between system memory and flash memory via an internal SRAM. Interrupts or status registers are used to identify the specific times at which this SRAM should be accessed using user programmable configuration registers.

The DMA peripheral bus optimizes data transfers to the flash memory and PHY during indirect transfers.

DMA Controller Implementation

The SRC and DST DMA controller has the same programming model as the CSU DMA in the AMD Zynq™ UltraScale+™ MPSoC.

The data read from the flash memory by the SRC DMA is put in a buffer for the DST DMA to access and write out to system memory using the controller's AXI master interface.