The following steps are for configuring the controller when it is powered on or after system or software reset.
- Choose the operating mode:Note: The sample point position programming follows the industry standard.
- Normal—write 0s to the [LBACK], [SNOOP], and [SLEEP] bits in the MSR. Write required value for [BRS] and [DAR] fields in the Mode_Select register.
- Sleep—write 1 to [SLEEP] bit and 0 to [LBACK] and [SNOOP]. Write required value for [BRS] and [DAR].
- Loopback—write 1 to [LBACK] and 0 to [SLEEP] and [SNOOP] bits. Write required value for [BRS].
- Snoop—write 1 to [SNOOP] bit and 0 to [LBACK] and [SLEEP].
- Configure the Transfer Layer Configuration registers.Important: For proper operation, ensure that all CAN FD nodes in the network are programmed to have the same arbitration phase bit rate, data phase bit rate, arbitration phase sample point position, and data phase sample point position.
- Program the ArbPhase_BaudRate prescale register (nominal) and the ArbPhase_BitTiming register (nominal) with the value calculated for the particular arbitration phase bit rate.
- Program the
registers with the value to achieve desired data phase bit rate.
Note: The bit rate configured for the data phase must be higher than or equal to the bit rate configured for the arbitration phase. The Transfer Layer Configuration registers can be changed only when the SW_Reset [CEN] bit is 0.Note: For operation with ArbPhase_BaudRate [BRP] = 0 (prescalar value = 1), set both [BRP] for nominal and data phase as 1 (register value = 0). Additionally, software needs to program the Mode_Select register bit  as follows (equivalent to [BRP_1_EN]):
- The DataPhase_BaudRate register also contains [TDC] control field.
- Set bit  = 1 when [BRP] = 1
- Set bit  = 0 when [BRP] != 1
- Configure the Acceptance Filter registers (AFR, AFMR, AFIR) to
- Write a 0 to the UAF bit in the register corresponding to the Acceptance Filter Mask and the ID register pair to be configured.
- Write the required mask information to the Acceptance Filter Mask register.
- Write the required ID information to the Acceptance Filter ID register.
- Write 1 to the UAF bit corresponding to the Acceptance Filter Mask and ID register pair.
- Repeat the steps for each Acceptance Filter Mask and ID register pair.
- To enable RX buffer 1, arrange the Filter Mask and ID
register as per the requirement. The [RXFP] field in the RX buffer
Watermark register also needs to be set accordingly to a value less
- Program the Interrupt Enable registers as per requirements.
- Enable the protocol controller by writing a 1 to SW_Reset [CEN]. After the occurrence of 11 consecutive recessive bits, the controller clears the Status [CONFIG] bit to 0 and sets other appropriate mode status bit in the Status register.
Recommended: If the [CEN] bit is cleared during the controller operation, then reset the controller, too.
Recommended: The [LBACK], [SLEEP], and [SNOOP] bits should never be set to 1 at the same time.