Control Registers

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

The IPI control registers are summarized in the following table. Access to the registers are controlled by the LPD_XPPU protection unit and the IPI (see Versal Adaptive SoC Register Reference (AM012)).

Table 1. IPI Control Registers
Register Name Offset Address Access Type Lockable Description
APB_ERR_CTRL 0x0000 RW Yes APB address decode SLVERR error signal enable






R, W1C

All except ISR Access violation and ECC error interrupt status, mask, enable and disable
LOCK 0x0090 RWSO NA Locks write access to all IPI registers except the ISR
SAFETY_CHK 0x0030 RW No Safety check registers





R NA Address and ID of error transaction





0x0040+ R NA

SMID  identification for:
PSM read/write
PSM read-only
PMC read/write
PMC read-only




0x0050+ RW Yes System management identification for software defined sources
IPI_ECC_CTRL 0x0094 RW Yes ECC control




0x0098+ R Yes First failing address, data and ECC register access with correctable error




0x00A4+ R Yes First failing address, data and ECC register access with un-correctable error




0x00B0+   Yes Fault injection count, data, and syndrome










0x00BC+ RW Yes

Source agent message buffer TrustZone security access settings:
0: secure access required
1: non-secure

TZ_APER_INTR 0x00DC RW Yes Interrupt register security access settings for all agents

Register Write Lock Bit

The IPI registers can only be configured by a TrustZone secure transaction. The secure transaction is routed through the LPD_XPPU protection unit to make sure the transaction host has access privileges before it is allowed to reach the IPI programming interface with its additional restrictions.

Writes to the IPI registers can be blocked by setting the LOCK [ReqWrDis] lock bit = 1. Once this bit is set, it can only be cleared by a POR.

After the lock bit is set, many of the registers can no longer be written to until a POR occurs. The lockability of the registers is shown in the Control Registers table.