Controller Clock Start-up

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

During start-up, the controller and I/O operate at 400 kHz using the DIV_CLK. This is accomplished by setting SDx_REF_CLK to 200 MHz and the clock divider fields to 100h (divide by 512). After the software has determined the capabilities of the SD/eMMC device, it can reprogram the clock divider to generate the DIV_CLK to match the desired I/O clock frequency.

If this clock frequency is over 25 MHz, the software needs to program the DLL, the SD_DLL_REF_CLK, and configure the controller to use the clocks from the DLL. After the DLL has locked, clocking for the SCLK output and the RX/TX interface units can switch over to the DLL clock source.