Controller Interrupts

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The controller interrupts are latched into the OPSI.IRQ_Status register. The source for each interrupt is indicated in the following table.

Table 1. OSPI Flash Controller Interrupts
Interrupt Bit Interrupt Source Description
STIG Direct Indirect Non-DMA Indirect DMA Polling
IND_OP_DONE 2 ~ ~ Yes Yes ~ Indirect operation complete
WPROT_ATTEMPT 4 Yes         Write protect access attempted
ILLEGAL_ACCESS_DET 5           Illegal AHB slave interface access attempted
IND_RD_SRAM_FULL 12 ~ Yes       Indirect read partition overflow
POLL_EXP 13 ~ ~ ~ ~ Yes Polling time period counter expired
STIG_REQ_RDY 14 Yes ~ ~ ~ ~