Controller Registers

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The USB_2_CSR registers provide general control and status, transaction controls, and manages APB and host system error interrupts. The registers are located at base address 0xFF9D_0000 and are summarized in the following table.

Table 1. USB 2.0 Control and Status Registers
Register Name Offset Address Access Type Description
PHY_Reset_En 0x01C RW PHY reset output mask
Port_Cfg 0x034 RW Device characteristics
Jitter_Adjust 0x038 RW High-speed jitter adjustment
Int_Endian 0x040 RW Set = 0; little endian
APB_Ctrl 0x060 RW APB slave error enable


            ISR
        


            IMR
        


            IER
        


            IDR
        

0x064
0x068
0x06C
0x070

W1C
R
W
W

APB address decode and host system error interrupts