Controller Registers

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2023-10-05
Revision
1.6 English

The USB_CSR registers provide general control and status, transaction controls, and manages APB and host system error interrupts. The registers are located at base address 0xFF9D_0000 and are summarized in the following table.

Table 1. USB 2.0 Control and Status Registers
Register Name Offset Address Access Type Description
0x01C RW PHY reset output mask
0x034 RW Device characteristics
0x038 RW High-speed jitter adjustment
0x040 RW Set = 0; little endian
0x060 RW APB programming interface error enable




0x064
0x068
0x06C
0x070

W1C
R
W
W

APB address decode and host system error interrupts